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MACH211SP-10 Dataheets PDF



Part Number MACH211SP-10
Manufacturers Advanced Micro Devices
Logo Advanced Micro Devices
Description High-Density EE CMOS Programmable Logic
Datasheet MACH211SP-10 DatasheetMACH211SP-10 Datasheet (PDF)

FINAL COM’L: -7.5/10/12/15/20 IND: -10/12/14/18/24 MACH211SP-7/10/12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS s JTAG-Compatible, 5-V in-system programming s 44 Pins s 64 Macrocells s 7.5 ns tPD Commercial 10 ns tPD Industrial s 133 MHz fCNT s 34 Bus-Friendly™ Inputs and I/Os s Peripheral Component Interconnect (PCI) compliant (-7/-10) s Programmable power-down mode s s s s 32 Outputs 64 Flip-flops; 2 clock choices 4 “PAL26V16” blocks with buried macrocells Impr.

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FINAL COM’L: -7.5/10/12/15/20 IND: -10/12/14/18/24 MACH211SP-7/10/12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS s JTAG-Compatible, 5-V in-system programming s 44 Pins s 64 Macrocells s 7.5 ns tPD Commercial 10 ns tPD Industrial s 133 MHz fCNT s 34 Bus-Friendly™ Inputs and I/Os s Peripheral Component Interconnect (PCI) compliant (-7/-10) s Programmable power-down mode s s s s 32 Outputs 64 Flip-flops; 2 clock choices 4 “PAL26V16” blocks with buried macrocells Improved routing over the MACH210 IN-SYSTEM PROGRAMMING In-system programming allows the MACH211SP to be programmed while soldered onto a system board. Programming the MACH211SP in-system yields numerous benefits at all stages of development: prototyping, manufacturing, and in the field. Since insertion into a programmer isn’t needed, multiple handling steps and the resulting bent leads are eliminated. The design can be modified in-system for design changes and debugging while prototyping, programming boards in production, and field upgrades. The MACH211SP offers advantages not available in other CPLD architectures with in-system programming. MACH devices have extensive routing resources for pin-out retention; design changes resulting in pin-out changes for other CPLDs cancel the advantages of in-system programming. The MACH211SP can be employed in any JTAG (IEEE 1149.1) compliant chain. GENERAL DESCRIPTION The MACH211SP is a member of AMD’s EE CMOS Performance Plus MACH® 2 device family. This device has approximately six times the logic macrocell capability of the popular PAL22V10 without loss of speed. The MACH211SP consists of four PAL® blocks interconnected by a programmable switch matrix. The four PAL blocks are essentially “PAL26V16” structures complete with product-term arrays and programmable macrocells, which can be programmed as high speed or low power, and buried macrocells. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH211SP has two kinds of macrocell: output and buried. The MACH211SP output macrocell provides registered, latched, or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All output macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input. The MACH211SP has dedicated buried macrocells which, in addition to the capabilities of the output macrocell, also provide input registers or latches for use in synchronizing signals and reducing setup time requirements. The MACH211SP is an enhanced version of the MACH211, adding the JTAG-compatible in-system programming feature. Publication# 20405 Rev: B Amendment/0 Issue Date: February 1996 BLOCK DIAGRAM I/O0–I/O7 8 I/O Cells 8 Macrocells 8 8 Macrocells I/O Cells 8 Macrocells I/O8–I/O15 8 8 8 Macrocells 2 OE 52 x 68 AND Logic Array and Logic Allocator 26 Switch Matrix 26 52 x 68 AND Logic Array and Logic Allocator OE Macrocells 8 I/O Cells 8 8 Macrocells 8 OE 52 x 68 AND Logic Array and Logic Allocator 26 26 52 x 68 AND Logic Array and Logic Allocator OE Macrocells 8 I/O Cells 8 8 Macrocells 8 2 2 I/O24–I/O31 I/O16–I/O23 CLK0/I0 CLK1/I1 20405B-1 2 MACH211SP-7/10/12/15/20 CONNECTION DIAGRAM MACH211SP Top View 44-Pin PLCC I/O31 I/O30 I/O29 6 I/O5 I/O6 I/O7 TDI CLK0/I0 GND TCK I/O8 I/O9 I/O10 I/O11 7 8 9 10 11 12 13 14 15 16 17 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 I/O27 I/O26 I/O25 I/O24 TDO GND CLK1/I1 TMS I/O23 I/O22 I/O21 18 19 20 21 22 23 24 25 26 27 28 I/O12 I/O13 I/O14 I/O15 GND I/O16 I/O17 I/O18 I/O19 I/O20 VCC I/O28 GND I/O4 I/O3 I/O2 I/O1 I/O0 VCC 20405B-2 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I I/O = Input = Input/Output TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out VCC = Supply Voltage MACH211SP-7/10/12/15/20 3 CONNECTION DIAGRAM MACH211SP Top View 44-Pin TQFP I/O5 I/O6 I/O7 TDI CLK0/I0 GND TCK I/O8 I/O9 I/O10 I/O11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 TDO GND CLK1/I1 TMS I/O23 I/O22 I/O21 I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20 20405B-3 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I I/O VCC = Input = Input/Output = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out 4 MACH211SP-7/10/12/15/20 ORDERING INFORMATION Commercial Products AMD programmable logic products for commercial applications are available.


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