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M66281FP Dataheets PDF



Part Number M66281FP
Manufacturers Mitsubishi
Logo Mitsubishi
Description 5120 x 8-BIT x 2 LINE MEMORY
Datasheet M66281FP DatasheetM66281FP Datasheet (PDF)

MITSUBISHI M66281FP 5120 x 8-BIT x 2 LINE MEMORY DESCRIPTION The M66281FP is high speed line memory that uses high performance silicon gate CMOS process technology and adopts the FIFO (First In First Out) structure consisting of 5120 words x 8 bits x 2. Since memory is available to simultaneously output 1 line delay and 2 line delay data, the M66281FP is optimal for the compensation of data of multiple lines. FEATURES • • • • • • • • • • Memory configuration 5120 words x 8 bits.

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MITSUBISHI M66281FP 5120 x 8-BIT x 2 LINE MEMORY DESCRIPTION The M66281FP is high speed line memory that uses high performance silicon gate CMOS process technology and adopts the FIFO (First In First Out) structure consisting of 5120 words x 8 bits x 2. Since memory is available to simultaneously output 1 line delay and 2 line delay data, the M66281FP is optimal for the compensation of data of multiple lines. FEATURES • • • • • • • • • • Memory configuration 5120 words x 8 bits x 2 (dynamic memory) High speed cycle 25 ns (Min.) High speed access 18 ns (Max.) Output hold 3 ns (Min.) Reading and writing operations can be completely carried out independently and asynchronously. Variable length delay bit Input/output TTL direct connection allowable Output 3 states Q00 – Q07 1 line delay Q10 – Q17 2 line delay APPLICATION • Digital copying machine, laser beam printer, high speed facsimile, etc. When write reset input WRESB is set to "L", the write address counter of memory only for 1 line delay data is initialized. When read enable input REB is set to "L", the contents of memory only for 1 line delay data are output to data outputs Q00 to Q07 and the contents of memory only for 2 line delay data are output to Q10 to Q17 in synchronization with a rising edge of read clock input RCK to perform reading operation. When this is the case, the read address counters of memory only for 1 line delay data and memory only for 2 line delay data are incremented simultaneously. In addition, data of Q00 to Q07 is written into memory only for 2 line delay data in synchronization with a rising edge of RCK. When this is the case, the write address counter of memory only for 2 line delay data is then incremented. When REB is set to "H", operation for reading data from memory only for 1 line delay and from memory only for 2 line delay data is inhibited and the read address counter of each memory stops. Outputs Q00 to Q07 and Q10 to Q17 are placed in a high impedance state. In addition, the write address counter of memory only for 2 line delay data then stops. When read reset input RRESB is set to "L", the read address counters of memory only for 1 line delay data as well as the write address counter and read address counter of memory only for 2 line delay data are then initialized. FUNCTION When write enable input WEB is set to "L", the contents of data inputs D0 to D7 are written into memory only for 1 line delay data in synchronization with a rising edge of write clock input WCK to perform writing operation. When this is the case, the write address counter of memory only for 1 line delay data is incremented simultaneously. When WEB is set to "H", the writing operation is inhibited and the write address counter of memory only for 1 line delay data stops. PIN CONFIGURATION (TOP VIEW) 35 WRESB 34 WCK 36 WEB 33 GND 38 NC 37 NC 32 VCC 26 NC 25 NC 24 NC 23 D5 22 D6 21 D7 20 GND 19 VCC 18 Q17 17 Q16 16 Q15 15 NC 31 D0 30 D1 29 D2 28 D3 27 D4 NC 39 RCK 40 RRESB 41 REB 42 GND 43 M66281FP VCC 44 Q00 45 Q01 46 Q02 47 NC 48 Q12 11 Q11 10 Q13 12 Q14 13 Q03 2 Q04 3 Q05 4 Q06 5 Q07 6 GND 7 VCC 8 Q10 9 NC 14 NC 1 Outline 48P6S-A(QFP) NC : No connection 1 2 Data inputs D0 to D7 Data outputs Q0 to Q7 Data outputs Q10 to Q17 29 28 27 23 22 21 45 46 47 2 3 4 5 6 9 10 11 12 13 16 17 18 Input buffer Output buffer 42 REB Read enable input 41 RRESB Read reset input Read control circuit Read address counter Write address counter Memory Array 5120 words x 8 bits x 2 Memory only for 1 line delay data Memory only for 2 line delay data 40 RCK Read clock input 7 GND 20 GND 33 GND 43 GND BLOCK DIAGRAM 31 30 Write enable input WEB 36 Write reset input WRESB 35 Write control circuit Write clock input WCK 34 VCC 8 VCC 19 VCC 32 MITSUBISHI 5120 x 8-BIT x 2 LINE MEMORY VCC 44 M66281FP MITSUBISHI M66281FP 5120 x 8-BIT x 2 LINE MEMORY ABSOLUTE MAXIMUM RATINGS (Ta=0 – 70 °C unless otherwise noted) Symbol Vcc VI VO Pd Tstg Parameter Supply voltage Input voltage Output voltage Power dispersion Storage temperature Conditions Ratings -0.3 – +4.6 -0.3 – VCC+0.3 -0.3 – VCC+0.3 540 -55 – 150 Unit V V V mW °C Value based on the GND pin Note Note : Ta=0 – 63˚C. Ta > 63˚C are derated at -9mW/˚C RECOMMENDED OPERATING CONDITIONS Symbol Vcc GND Topr Parameter Supply voltage Supply voltage Operating temperature Min. 2.7 0 Limits Typ. 3.15 0 Max. 3.6 70 Unit V V °C ELECTRICAL CHARACTERISTICS (Ta=0 – 70 °C, Vcc=2.7 – 3.6V, GND=0V unless otherwise noted) Symbol VIH VIL VOH VOL IIH Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage High-level input current Conditions Min. 2.0 VCC-0.4 0.4 WEB, WRESB, WCK, REB, RRESB, RCK, D0 – D7 WEB, WRESB, WCK, REB, RRESB, RCK, D0 – D7 1.0 Limits Typ. Max. 0.8 IOH = -4mA IOL = 4mA VI = VCC Unit V V V V µA IIL IOZH IOZL ICC CI CO Low-level input current Off-state high-level output current Off-state low-level outpu.


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