256 x 8-BIT MAIL-BOX
MITSUBISHI MITSUBISHI 〈DIGITAL 〈DIGITAL ASSP ASSP 〉 〉
M66220SP/FP M66220SP/FP
× 8-BIT MAIL-BOX 256256 × 8-BIT MAIL-BOX
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Description
MITSUBISHI MITSUBISHI 〈DIGITAL 〈DIGITAL ASSP ASSP 〉 〉
M66220SP/FP M66220SP/FP
× 8-BIT MAIL-BOX 256256 × 8-BIT MAIL-BOX
DESCRIPTION
The M66220 is a mail box that incorporates a complete CMOS shared memory cell of 256 × 8-bit configuration using high-performance silicon gate CMOS process technology, and is equipped with two access ports of A and B. Access ports A and B are equipped with independent addresses CS, WE and OE control pins and I/O pins to allow independent and asynchronous read/write operations from/to shared memory individually. This product also incorporates a port adjustment arbitration function in address contention from both ports.
PIN CONFIGURATION (Top view)
CHIP SELECT CSA → 1 INPUT WRITE ENABLE WEA → 2 INPUT NOT READY Not Ready A← 3 OUTPUT OUTPUT ENABLE OEA → INPUT A 0A → A 1A → A 2A → A PORT A3A → ADDRESS INPUT A 4A → A 5A → A 6A → A 7A → I/O0A ↔ I/O1A ↔ I/O2A ↔ ↔ A PORT I/O3A DATA I/O ↔ 4 A I/O I/O5A ↔ I/O6A ↔ I/O7A ↔ GND 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 VCC CHIP SELECT 41 ← CSB INPUT WRITE ENABLE 40 ← WEB INPUT 39 → Not Ready B NOT READY OUTPUT 38 ← OEB OUTPUT ENABLE INPUT 37 ← A0B 36 ← A1B 35 ← A2B 34 ← A3B B PORT ADDRESS 33 ← A4B INPUT 32 ← A5B 31 ← A6B 30 ← A7B 29 ↔ I/O7B 28 ↔ I/O6B 27 ↔ I/O5B 26 ↔ I/O4B B PORT DATA I/O 25 ↔ I/O3B 24 ↔ I/O2B 23 ↔ I/O1B 22 ↔ I/O0B
FEATURES
Memory configuration...
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