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M5M5Y5672TG-25 Dataheets PDF



Part Number M5M5Y5672TG-25
Manufacturers Mitsubishi
Logo Mitsubishi
Description 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
Datasheet M5M5Y5672TG-25 DatasheetM5M5Y5672TG-25 Datasheet (PDF)

2001.May Rev.0.1 MITSUBISHI LSIs Advanced Information Notice: This is not final specification. Some parametric limits are subject to change. M5M5Y5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM Synchronous circuitry allows for precise cycle control triggered by a positive edge clock transition. Synchronous signals include : all Addresses, all Data Inputs, all Chip Enables (E1#, E2, E3), Address Advance/Load (ADV), Byte Write Enables (BWa#, BWb#, BWc#, BWd#, BWe#, BWf#, BWg#.

  M5M5Y5672TG-25   M5M5Y5672TG-25


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2001.May Rev.0.1 MITSUBISHI LSIs Advanced Information Notice: This is not final specification. Some parametric limits are subject to change. M5M5Y5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM Synchronous circuitry allows for precise cycle control triggered by a positive edge clock transition. Synchronous signals include : all Addresses, all Data Inputs, all Chip Enables (E1#, E2, E3), Address Advance/Load (ADV), Byte Write Enables (BWa#, BWb#, BWc#, BWd#, BWe#, BWf#, BWg#, BWh#), Echo Clock outputs (CQ1, CQ1#, CQ2, CQ2#) and Read/Write (W#). Write operations are controlled by the eight Byte Write Enables (BWa# - BWh#) and Read/Write(W#) inputs. All writes are conducted with on-chip synchronous self-timed write circuitry. The Echo Clocks are delayed copies of the RAM clock, CLK. Echo Clocks are designed to track changes in output driver delays due to variance in die temperature and supply voltage. The ZQ pin supplied with selectable impedance drivers, allows selection between nominal drive strength (ZQ LOW) for multi-drop bus application and low drive strength (ZQ floating or HIGH) point-to-point applications. The sense of two User-Programmable Chip Enable inputs (E2, E3), whether they function as active LOW or active HIGH inputs, is determined by the state of the programming inputs, EP2 and EP3. The Linear Burst order (LBO#) is DC operated pin. LBO# pin will allow the choice of either an interleaved burst, or a linear burst. All read, write and deselect cycles are initiated by the ADV Low input. Subsequent burst address can be internally generated as controlled by the ADV HIGH input. DESCRIPTION The M5M5Y5672TG is a family of 18M bit synchronous SRAMs organized as 262144-words by 72-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Mitsubishi's SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability. M5M5Y5672TG operates on a single 1.8V power supply and are 1.8V CMOS compatible. FEATURES • Fully registered inputs and outputs for pipelined operation • Fast clock speed: 250, 225, and 200 MHz • Fast access time: 2.6, 2.8, 3.2 ns • Single 1.8V +150/-100mV power supply VDD • Separate VDDQ for 1.8V I/O • Individual byte write (BWa# - BWh#) controls may be tied LOW • Single Read/Write control pin (W#) • Echo Clock outputs track data output drivers • ZQ mode pin for user-selectable output drive strength • 2 User programmable chip enable inputs for easy depth expansion • Linear or Interleaved Burst Modes • JTAG boundary scan support APPLICATION High-end networking products that require high bandwidth, such as switches and routers. FUNCTION PACKAGE Bump M5M5Y5672TG 209(11X19) bump BGA Body Size 14mm X 22mm Bump Pitch 1mm PART NAME TABLE Part Name M5M5Y5672TG -25 M5M5Y5672TG -22 M5M5Y5672TG -20 Frequency 250MHz 225MHz 200MHz Access 2.6ns 2.8ns 3.2ns Cycle 4.0ns 4.4ns 5.0ns Active Current (max.) 550mA 500mA 450mA Standby Current (max.) 20mA 20mA 20mA 1 MITSUBISHI ELECTRIC Advanced Information M5M5Y5672TG REV.0.1 MITSUBISHI LSIs M5M5Y5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM BUMP LAYOUT(TOP VIEW) 209 bump BGA 1 A B C D E F G H J K L M N P R T U V W DQg DQg DQg DQg DQPg DQc DQc DQc DQc CQ2 DQh DQh DQh DQh DQPd DQd DQd DQd DQd 2 DQg DQg DQg DQg DQPc DQc DQc DQc DQc CQ2# DQh DQh DQh DQh DQPh DQd DQd DQd DQd 3 A6 BWc# BWh# VSS VDDQ VSS VDDQ VSS VDDQ CLK VDDQ VSS VDDQ VSS VDDQ VSS NC A5 TMS 4 E2 BWg# BWd# NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A3 A4 TDI 5 A7 NC NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC A16 A2 6 ADV W# E1# MCL VDD ZQ EP2 EP3 MCH MCL MCH MCL MCH MCL VDD LBO# A15 A1 A0 7 A8 A17 NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC A13 A14 8 E3 BWb# BWe# NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A11 A12 TDO 9 A9 BWf# BWa# VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC A10 TCK 10 DQb DQb DQb DQb DQPf DQf DQf DQf DQf CQ1# DQa DQa DQa DQa DQPa DQe DQe DQe DQe 11 DQb DQb DQb DQb DQPb DQf DQf DQf DQf CQ1 DQa DQa DQa DQa DQPe DQe DQe DQe DQe Note1. MCH means “Must Connect High”. MCH should be connected to HIGH. Note2. MCL means “Must Connect Low”. MCL should be connected to LOW. 2 MITSUBISHI ELECTRIC Advanced Information M5M5Y5672TG REV.0.1 MITSUBISHI LSIs M5M5Y5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM BLOCK DIAGRAM VDD VDDQ A0 A1 A2~17 LBO# 18 18 ADDRESS REGISTER A1 D1 A0 D0 LINEAR/ INTERLEAVED BURST COUNTER Q1 A0' Q0 A1' 16 18 CLK WRITE ADDRESS REGISTER1 WRITE ADDRESS REGISTER2 18 ADV BWa# BWb# BWc# BWd# BWe# BWf# BWg# BWh# W# 128Kx72 WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BYTE a | BYTE h WRITE DRIVERS MEMORY ARRAY 72 INPUT REGISTER1 INPUT REGISTER0 DQa DQPa DQb DQPb DQc DQPc DQd DQPd DQe DQPe DQf DQPf DQg DQPg DQh DQPh OUTPUT REGISTERS ECHO CLOCK OUTPUT REGISTERS READ LOGIC CHIP ENABLE CONTROL LOGIC ECHO CLOCK OUTPU.


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