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M5M5W816WG-70HI Dataheets PDF



Part Number M5M5W816WG-70HI
Manufacturers Mitsubishi
Logo Mitsubishi
Description 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Datasheet M5M5W816WG-70HI DatasheetM5M5W816WG-70HI Datasheet (PDF)

2001.6.11 Ver. 3.1 MITSUBISHI LSIs M5M5W816WG - 70HI, 85HI DESCRIPTION The M5M5W816 is a f amily of low v oltage 8-Mbit static RAMs organized as 524288-words by 16-bit, f abricated by Mitsubishi's high-perf ormance 0.18µm CMOS technology . The M5M5W816 is suitable f or memory applications where a simple interf acing , battery operating and battery backup are the important design objectiv es. M5M5W816WG is packaged in a CSP (chip scale package), with the outline of 7.5mm x 8.5mm, ball matrix o.

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2001.6.11 Ver. 3.1 MITSUBISHI LSIs M5M5W816WG - 70HI, 85HI DESCRIPTION The M5M5W816 is a f amily of low v oltage 8-Mbit static RAMs organized as 524288-words by 16-bit, f abricated by Mitsubishi's high-perf ormance 0.18µm CMOS technology . The M5M5W816 is suitable f or memory applications where a simple interf acing , battery operating and battery backup are the important design objectiv es. M5M5W816WG is packaged in a CSP (chip scale package), with the outline of 7.5mm x 8.5mm, ball matrix of 6 x 8 (48ball) and ball pitch of 0.75mm. It giv es the best solution f or a compaction of m ounting area as well as f lexibility of wiring pattern of printed circuit boards. Those are summarized in the part name table below. PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM FEATURES - Single 2.7~3.0V power supply - Small stand-by current: 0.1µA (2V, ty p.) - No clocks, No ref resh - Data retention supply v oltage =2.0V - All inputs and outputs are TTL compatible. - Easy memory expansion by S1#, S2, BC1# and BC2# - Common Data I/O - Three-state outputs: OR-tie capability - OE prev ents data contention in the I/O bus - Process technology : 0.18µm CMOS - Package: 48ball 7.5mm x 8.5mm CSP Version, Operating temperature Part name Power Supply Access time max. 70ns Stand-by c urrent (µA @ Vcc=3.0V) Ratings (max.) * Ty pical 25°C 40°C 25°C 40°C 70°C 85°C 1.0 2 4 20 40 Activ e current Icc1 * ( ty p.) 40mA (10MHz) 10mA (1MHz) I-version -40 ~ +85°C M5M5W816WG -70HI 2.7 ~ 3.0V M5M5W816WG -85HI 0.5 85ns * Typical parameter indicates the value for the center of distribution, and is not 100% tested. PIN CONFIGURATION (TOP VIEW) 1 A B C D E F G H BC1# 2 OE# 3 A0 4 A1 5 A2 6 S2 DQ16 BC2# A3 A4 S1# DQ1 Pin DQ14 DQ15 A5 A6 DQ2 DQ3 Function Address input Chip select input 1 Chip select input 2 Write control input Output enable input Lower By te (DQ1 ~ 8) Upper By te (DQ9 ~ 16) Power supply Ground supply A0 ~ A18 S1# S2 W# OE# BC1# BC2# Vcc GND DQ1 ~ DQ16 Data input / output GND DQ13 A17 A7 DQ4 VCC VCC DQ12 NC or GND A16 DQ5 GND D Q 11 DQ10 A14 A15 DQ7 DQ6 DQ9 N.C. A12 A13 W# DQ8 A18 A8 A9 A10 A11 N .C . Outline : 48F7Q NC : No Connection *Don't connect E3 ball to voltage level more than 0V MITSUBISHI ELECTRIC 1 2001.6.11 Ver. 3.1 MITSUBISHI LSIs M5M5W816WG - 70HI, 85HI FUNCTION The M5M5W816WG is organized as 524288-words by 16-bit. These dev ices operate on a single +2.7~3.0V power supply , and are directly TTL compatible to both input and output. Its f ully static circuit needs no clocks and no ref resh, and makes it usef ul. The operation mode are determined by a combination of the dev ice control inputs BC1# , BC2# , S1#, S2 , W# and OE#. Each mode is summarized in the f unction table. A write operation is executed whenev er the low lev el W# ov erlaps with the low lev el BC1# and/or BC2# and the low lev el S1# and the high lev el S2. The address(A0~A18) must be set up bef ore the write cy c le and must be stable during the entire cycle. A read operation is executed by s etting W# at a high lev el and OE# at a low lev el while BC1# and/or BC2# and S1# and S2 are in an activ e state(S1#=L,S2=H). When setting BC1# at the high lev el and other pins are in an activ e stage , upper-by t e are in a selectable mode in which both reading and writing are enabled, and lower-by t e are in a non-selectable mode. And when setting BC2# at a high lev el and other pins are in an activ e stage, lower-by t e are in a selectable mode and upper-by te are in a nonselectable mode. PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM When setting BC1# and BC2# at a high lev el or S1# at a high lev el or S2 at a low lev el, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1#, BC2# and S1#, S2. The power supply c urrent is reduced as low as 0.1µA(25°C, ty pical), and the memory data can be held at +2.0V power supply , enabling battery back-up operation during power f ailure or power-down operation in the non-selected mode. FUNCTION TABLE S1# S2 BC1# BC2# W# OE# Mode Non selection Non selection Non selection Non selection DQ1~8 DQ9~16 BLOCK DIAGRAM A0 A1 MEMORY ARRAY 524288 WORDS x 16 BITS A 17 A 18 S1# S2 CLOCK GENERATOR H L H X L L L L L L L L L L L H X H H H H H H H H H X X X H L L L H H H L L L X X X H H H H L L L L L L X X X X L H H L H H L H H X X X X X L H X L H X L H Write Read Write Read Write Read High-Z High-Z High-Z High-Z Din Dout High-Z High-Z High-Z High-Z Din Dout High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Din Dout High-Z Din Dout High-Z Icc Standby Standby Standby Standby Activ e Activ e Activ e A.


M5M5W816WG-10LI M5M5W816WG-70HI M5M5W816WG-85H


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