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M5M5V208KR-70L Dataheets PDF



Part Number M5M5V208KR-70L
Manufacturers Mitsubishi
Logo Mitsubishi
Description 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
Datasheet M5M5V208KR-70L DatasheetM5M5V208KR-70L Datasheet (PDF)

'97.3.21 MITSUBISHI LSIs M5M5V208FP,VP,RV,KV,KR -70L , -85L, -10L , -12L, -70LL, -85LL, -10LL, -12LL 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM DESCRIPTION The M5M5V208 is 2,097,152-bit CMOS static RAM organized as 262,144-words by 8-bit which is fabricated using high-performance quadruple-polysilicon and double metal CMOS technology. The use of thin film transistor(TFT) load cells and CMOS periphery results in a high density and low power static RAM. The M5M5V208 is designed for me.

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'97.3.21 MITSUBISHI LSIs M5M5V208FP,VP,RV,KV,KR -70L , -85L, -10L , -12L, -70LL, -85LL, -10LL, -12LL 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM DESCRIPTION The M5M5V208 is 2,097,152-bit CMOS static RAM organized as 262,144-words by 8-bit which is fabricated using high-performance quadruple-polysilicon and double metal CMOS technology. The use of thin film transistor(TFT) load cells and CMOS periphery results in a high density and low power static RAM. The M5M5V208 is designed for memory applications where high reliability, large storage, simple interfacing and battery back-up are important design objectives. The M5M5V208VP,RV,KV,KR are packaged in a 32-pin thin small outline package which is a high reliability and high density surface mount device(SMD).Two types of devices are available. VP,KV(normal lead bend type package),RV,KR(reverse lead bend type package). Using both types of devices, it becomes very easy to design a printed circuit board. PIN CONFIGURATION (TOP VIEW) A17 1 A16 2 A14 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 DQ1 13 DQ2 14 DQ3 15 (0V)GND 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 FEATURE Type M5M5V208FP,VP,RV,KV,KR-70L M5M5V208FP,VP,RV,KV,KR-85L M5M5V208FP,VP,RV,KV,KR-10L M5M5V208FP,VP,RV,KV,KR-12L M5M5V208FP,VP,RV,KV,KR-70LL M5M5V208FP,VP,RV,KV,KR-85LL M5M5V208FP,VP,RV,KV,KR-10LL M5M5V208FP,VP,RV,KV,KR-12LL Access Power supply current time Active Stand-by (max) (max) (max) 70ns 85ns 100ns 120ns 70ns 85ns 100ns 120ns 27mA (Vcc=3.6V) VCC(3V) A15 S2 W A13 A8 A9 A11 OE A10 S1 DQ8 DQ7 DQ6 DQ5 DQ4 Outline 32P2M-A(FP) 60µA (Vcc=3.6V) 10µ A (Vcc=3.6V) • Single 2.7 ~ 3.6V power supply • Operating temperature of 0 to +70°C • No clocks, No refresh • All inputs and outputs are TTL compatible. • Easy memory expansion and power down by S1 & S2 • Data retention supply voltage=2.0V • Three-state outputs: OR-tie capability • OE prevents data contention in the I/O bus • Common Data I/O • Battery backup capability • Small stand-by current · · · · · · · · · · 0.3µA(typ.) A11 A9 A8 A13 W S2 A15 Vcc A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 M5M5V208VP,KV 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 S1 DQ8 DQ7 DQ6 DQ5 DQ4 GND DQ3 DQ2 DQ1 A0 A1 A2 A3 Outline 32P3H-E(VP), 32P3K-B(KV) PACKAGE M5M5V208FP : 32 pin 525 mil SOP M5M5V208VP,RV : 32pin 8 X 20 mm2 TSOP M5M5V208KV,KR : 32pin 8 X 13.4 mm2 TSOP S2 W A4 A5 A6 A7 A12 A14 A16 A17 Vcc A15 A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 M5M5V208RV,KR 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A3 A2 A1 A0 DQ1 DQ2 DQ3 GND DQ4 DQ5 DQ6 DQ7 DQ8 S1 A10 OE APPLICATION Small capacity memory units Battery operating system Handheld communiation tools Outline 32P3H-F(RV), 32P3K-C(KR) MITSUBISHI ELECTRIC 1 '97.3.21 MITSUBISHI LSIs M5M5V208FP,VP,RV,KV,KR -70L , -85L, -10L , -12L, -70LL, -85LL, -10LL, -12LL 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM FUNCTION The operation mode of the M5M5V208 is determined by a combination of the device control inputs S1, S 2, W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S1 and the high level S2. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W, S1 or S2, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable OE directly controls the output stage. Setting the OE at a high level,the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is executed by setting W at a high level and OE at a low level while S1 and S 2 are in an active state (S1 = L ,S2 = H). When setting S1 at a high level or S2 at a low level, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by S1 or S2. The power supply current is reduced as low as the stand-by current which is specified as Icc3 or Icc4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the nonselected mode. FUNCTION TABLE S1 X H L L L S2 L X H H H W X X L H H OE X X X L H Mode Non selection Non selection Write Read DQ High-impedance High-impedance D IN D OUT High-impedance Icc Standby Standby Active Active Active BLOCK DIAGRAM * A4 A5 A6 A7 A12 A14 A16 A17 A15 8 7 6 5 4 3 2 1 31 16 15 14 13 12 11 10 9 7 262144 WORDS X 8 BITS 512 ROWS X 128 COLUMNS X 32 BLOCKS 21 22 23 25 26 27 28 29 13 14 15 17 18 19 20 21 * DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 A0 A1 A2 A3 A10 A11 A9 A8 A13 12 11 10 9 23 25 26 27 28 20 19 18 17 5 31 30 1 6 2 32 3 4 8 32 24 30 22 29 CLOCK GENERATOR W S1 S2 OE VCC (3V) 24 16 GND (0V) *Pin numbers inside dotted line show .


M5M5V208KR-12LL-W M5M5V208KR-70L M5M5V208KR-70L-W


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