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M5M54R04AJ-12 Dataheets PDF



Part Number M5M54R04AJ-12
Manufacturers Mitsubishi
Logo Mitsubishi
Description 4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
Datasheet M5M54R04AJ-12 DatasheetM5M54R04AJ-12 Datasheet (PDF)

MITSUBISHI LSIs 1998.11.30 Ver.B PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change M5M54R04AJ-10,-12,-15 4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM PIN CONFIGURATION (TOP VIEW) DESCRIPTION The M5M54R04AJ is a family of 1048576-word by 4-bit static RAMs, fabricated with the high performance CMOS A0 1 A1 2 application. A2 3 address inputs A3 4 These devices operate on a single 3.3V supply, and are A 4 5 select directly TTL compatible. .

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MITSUBISHI LSIs 1998.11.30 Ver.B PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change M5M54R04AJ-10,-12,-15 4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM PIN CONFIGURATION (TOP VIEW) DESCRIPTION The M5M54R04AJ is a family of 1048576-word by 4-bit static RAMs, fabricated with the high performance CMOS A0 1 A1 2 application. A2 3 address inputs A3 4 These devices operate on a single 3.3V supply, and are A 4 5 select directly TTL compatible. They include a power down chip input S 6 data inputs/ DQ 1 7 feature as well. outputs(3.3V) VCC 8 (0V) GND 9 FEATURES data inputs/ •Fast access time M5M54R04AJ-10 ... 10ns(max) DQ2 10 outputs M5M54R04AJ-12 ... 12ns(max) write control W 11 input M5M54R04AJ-15 ... 15ns(max) A5 12 A6 13 •Single +3.3V power supply address A7 14 inputs •Fully static operation : No clocks, No refresh A8 15 •Common data I/O A9 16 •Easy memory expansion by S •Three-state outputs : OR-tie capability Outline •OE prevents data contention in the I/O bus •Directly TTL compatible : All inputs and outputs silicon gate process and designed for high speed 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A19 A18 A17 address inputs A16 A15 output enable OE input DQ4 data inputs/ GND (0V) outputs VCC (3.3V) DQ3 data inputs/ outputs A14 A13 address A12 inputs A11 A10 NC 32P0K(SOJ) APPLICATION High-speed memory units PACKAGE M5M54R04AJ : 32pin 400mil SOJ BLOCK DIAGRAM A0 A1 A2 A3 adress inputs 1 2 3 4 MEMORY ARRAY 1024 ROWS 4096 COLUMNS 7 10 23 26 DQ1 DQ2 DQ3 DQ4 data inputs/ outputs A4 5 A5 12 A6 13 A7 14 A8 15 A9 16 S 6 COLUMN I/O CIRCUITS COLUMN ADDRESS DECODERS 8 24 W 11 COLUMN INPUT BUFFERS VCC (3.3V) 9 25 OE 27 GND (0V) 18 19 20 21 22 28 29 30 31 32 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 address inputs MITSUBISHI ELECTRIC 1 MITSUBISHI LSIs M5M54R04AJ-10,-12,-15 4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM FUNCTION The operation mode of the M5M54R04AJ is determined by a combination of the device control inputs S, W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S. The address must be set-up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W or S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is excuted by setting W at a high level and OE at a low level while S are in an active state (S=L). When setting S at high level, the chip is in a nonselectable mode in which both reading and writing are disable. In this mode, the output stage is in a highimpedance state, allowing OR-tie with other chips and memory expansion by S. Signal-S controls the power-down feature. When S goes high, power dissapation is reduced extremely. The access time from S is equivalent to the address access time. FUNCTION TABLE S H L L L W X L H H OE X X L H Mode Non selection Write Read DQ High-impedance Din Dout High-impedance Icc Stand by Active Active Active ABSOLUTE MAXIMUM RATINGS Symbol V cc VI VO Pd T opr T stg * Pulse Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Conditions With respect to GND Ratings - 2.0 * ~ 4.6 * - 2.0 ~ VCC+0.5 - 2.0*~ VCC 1000 0 ~ 70 - 10 ~ 85 - 65 ~ 150 +10% - 5% Unit V V V mW °C °C °C Ta=25°C Tstg(bias) Storage temperature(bias) Storage temperature width≤3ns, In case of DC: - 0.5V DC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70°C, Vcc=3.3V Symbol VIH VIL VOH VOL II I OZ Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current Condition ,unless otherwise noted) Limits Min 2.0 2.4 0.4 2 2 Typ Max Vcc+0.3 0.8 Unit V V V V uA uA I OH = - 4mA IOL = 8mA VI= 0 ~ Vcc VI(S)=VIH Output current in off-state VI/O= 0 ~ Vcc Active supply current (TTL level) VI(S)=VIL other inpus=VIH or VIL Output-open(duty 100%) 10ns cycle AC 12ns cycle 15ns cycle DC 10ns cycle AC 12ns cycle 15ns cycle DC I CC1 I CC2 Stand by current (TTL level) VI(S)=VIH VI(S)=Vcc≥0.2V other inputs VI≤0.2V or VI ≥Vcc - 0.2V 190 180 160 90 90 70 60 40 10 mA mA I CC3 Stand by current mA Note 1: Direction for current flowing into an IC is positive (no mark). MITSUBISHI ELECTRIC 2 MITSUBISHI LSIs M5M54R04AJ-10,-12,-15 4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM CAPACITANCE (Ta=0~70°C, Vcc=3.3V Symbol CI CO Parameter Input capacitance Output capacitance +10% -5% ,unless otherwise noted) Test Condition Min Limit Typ Max 7 8 Unit pF pF V I =GND, V I =25mVrms,f=1MHz V O=GND, V O=25mVrms,f=1MHz Note 2: CI,CO are periodically sampled and are not 100% tested. AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C,.


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