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M5M44800CJ,TP-5,-6,-7, M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S -5S,-6S,-7S
FAST FAST PAGE PAGE MODE MODE 4194304-BIT 4194304-BIT (524288-WORD (524288-WORD BYBY 8-BIT) 8-BIT) DYNAMIC DYNAMIC RAM RAM
DESCRIPTION
This is a family of 524288-word by 8-bit dynamic RAMs, fabricated with the high performance CMOS process, and is ideal for largecapacity memory systems where high speed, low power dissipation, and low costs are essential. The use of double-layer metalization process technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is low enough for battery back-up application.
MITSUBISHI LSIs MITSUBISHI LSIs
PIN CONFIGURATION (TOP VIEW)
(5V)VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 NC 6 W 7 9 RAS 8 A9
28 VSS(0V) 27 DQ8 26 DQ7 25 DQ6 24 DQ5 23 CAS 22 OE 21 NC 20 A8 19 A7 18 A6 17 A5 16 A4 15 VSS(0V)
FEATURES
Type name
M5M44800CXX-5,-5S M5M44800CXX-6,-6S M5M44800CXX-7,-7S
RAS CAS Address OE Cycle Power access access access access time dissipation time time time time (max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
A0 10 A1 11 A2 12 A3 13 (5V)VCC 14
50 60 70
13 15 20
25 30 35
13 15 20
90 110 130
450 375 325
XX=J,TP
Outline 28P0K(400mil SOJ)
Standard 28pin SOJ, 28pin TSOP (II) Single 5V±10% supply Low stand-by power dissipation CMOS lnput level 5.5mW (Max) CMOS Input level 550µW (Max) * Operating power dissipation M5M44800Cxx-5,-5S 495mW (Max) M5M44800Cxx-6,-6S 413mW (Max) M5M44800Cxx-7,-7S 358mW (Max) Self refresh capability * Self refresh current 150µA(Max) Extended refresh capability Extended refresh current 150µA(Max) Fast page mode(1024-column random access),Read-modify-write, RAS-only refresh, CAS before RAS refresh, Hidden refresh capabilities. Early-write mode, CAS and OE to control output buffer impedance 1024 refresh cycles every 16.4ms (A0 ~A9) 1024 refresh cycles every 128ms (A0 ~A9) * * :Applicable to self refresh version (M5M44800CJ,TP-5S,-6S,-7S :option) only
(5V)VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 NC 6 W A9 7 9 RAS 8 A0 10 A1 11 A2 12 A3 13 (5V)VCC 14
28 VSS(0V) 27 DQ8 26 DQ7 25 DQ6 24 DQ5 23 CAS 22 OE 21 NC 20 A8 19 A7 18 A6 17 A5 16 A4 15 VSS(0V)
Outline 28P3Y-H(400mil TSOP Normal Bend) APPLICATION
Microcomputer memory, Refresh memory for CRT
NC:NO CONNECTION
PIN DESCRIPTION
Pin name A0~A9 DQ1~DQ8 RAS CAS W OE Vcc Vss Function Address inputs Data inputs/outputs Row address strobe input Column address strobe input Write control input Output enable input Power supply (+5V) Ground (0V)
1
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
FUNCTION
In addition to normal read, write, and read-modify-write operations the M5M44800CJ, TP provides a number of other functions, e.g., fast page mode, RAS-only refresh, and delayed-write. The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation Read Write (Early write) Write (Delayed write) Read-modify-write RAS only refresh Hidden refresh
CAS before RAS (Extended *) refresh
Inputs RAS ACT ACT ACT ACT ACT ACT ACT ACT NAC CAS ACT ACT ACT ACT NAC ACT ACT ACT DNC W NAC ACT ACT ACT DNC DNC DNC DNC DNC OE ACT DNC DNC ACT DNC ACT DNC DNC DNC
Row address Column address
Input/Output APD APD APD APD APD DNC DNC DNC DNC APD APD APD APD DNC DNC DNC DNC DNC Input OPN VLD VLD VLD DNC OPN DNC DNC DNC Output VLD OPN IVD VLD OPN VLD OPN OPN OPN
Refresh YES YES YES YES YES YES YES YES NO
Remark Fast page mode identical
Self refresh * Stand-by
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : invalid, APD : applied, OPN : open
BLOCK DIAGRAM
COLUMN ADDRESS STROBE INPUT CAS ROW ADDRESS RAS STROBE INPUT WRITE CONTROL INPUT W A0~A8
VCC (5V)
CLOCK GENERATOR CIRCUIT
VCC (5V) VSS (0V) VSS (0V) (8) DATA IN BUFFER
COLUMN DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
SENSE REFRESH AMPLIFIER & I /O CONTROL
ADDRESS INPUTS
ROW & COLUMN ADDRESS BUFFER
ROW A0~ A9 DECODER
MEMORY CELL (4194304BITS)
(8) DATA OUT BUFFER
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
DATA INPUTS / OUTPUTS
OE OUTPUT ENABLE INPUT
2
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Conditions With respect to VSS Ratings -1~7 -1~7 -1~7 50 1000 0~70 -65~150 Unit V V V mA mW ˚C ˚C
Ta=25˚C
RECOMMENDED OPERATING CONDITIONS (Ta=0~70˚C, unless otherwise noted)
Symbol VCC VSS VIH VIL Parameter Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage, all inputs Min 4.5 0 2.4 -0.5 * * Limits Nom 5.0 0 Max 5.5 0 6.0 0.8
(Note 1)
Unit V V V V
Note 1 .