Document
M5M44265CJ,TP-5,-6,-7, M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S -5S,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD 16-BIT) DYNAMIC RAM EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY BY 16-BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 262144-word by 16-bit dynamic RAMs with Hyper Page mode fuction, fabricated with the high performance CMOS process, and is ideal for the buffer memory systems of personal computer graphics and HDD where high speed, low power dissipation, and low costs are essential. The use of double-layer metalization process technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is low enough for battery back-up application. This device has 2CAS and 1W terminals with a refresh cycle of 512 cycles every 8.2ms.
MITSUBISHI LSIs MITSUBISHI LSIs
PIN CONFIGURATION (TOP VIEW)
(5V)VCC DQ1 DQ2 DQ3 DQ4 (5V)VCC DQ5 DQ6 DQ7 VSS(0V) DQ16 DQ15 DQ14 DQ13 VSS(0V) DQ12 DQ11 DQ10 DQ9 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS(0V)
1 2 3 4 5 6 7 8 9
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
FEATURES
Type name
M5M44265CXX-5,-5S M5M44265CXX-6,-6S M5M44265CXX-7,-7S RAS CAS access access time time (max.ns) (max.ns) OE Address access access time time (max.ns) (max.ns) Power Cycle dissipatime tion (min.ns) (typ.mW)
DQ8 10 NC 11 NC 12 W 13 RAS 14 NC 15 A0 16 A1 17 A2 18 A3 19
50 60 70
13 15 20
25 30 35
13 15 20
90 110 130
625 550 475
XX=J,TP
Standard 40pin SOJ, 44 pin TSOP (II) Single 5V±10% supply Low stand-by power dissipation CMOS Input level 5.5mW (Max) CMOS Input level 550µW (Max)* Operating power dissipation M5M44265Cxx-5,-5S 688mW (Max) M5M44265Cxx-6,-6S 605mW (Max) M5M44265Cxx-7,-7S 523mW (Max) Self refresh capability* Self refresh current 150µA (Max) Extended refresh capability Extended refresh current 150µA (Max) Hyper-page mode (512-column random access), Read-modifywrite, RAS-only refresh, CAS before RAS refresh, Hidden refresh capabilities. Early-write mode, OE and W to control output buffer impedance 512 refresh cycles every 8.2ms (A0~A8) 512 refresh cycles every 128ms (A0~A8)* Byte or word control for Read/Write operation (2CAS, 1W type) * : Applicable to self refresh version (M5M44265CJ,TP-5S,-6S,-7S : option) only
(5V)VCC 20
Outline 40P0K (400mil SOJ)
(5V)VCC DQ1 DQ2 DQ3 DQ4 (5V)VCC DQ5 DQ6 DQ7
1 2 3 4 5 6 7 8 9
44 43 42 41 40 39 38 37 36 35
VSS(0V) DQ16 DQ15 DQ14 DQ13 VSS(0V) DQ12 DQ11 DQ10 DQ9
DQ8 10
APPLICATION
Microcomputer memory, Refresh memory for CRT, Frame Buffer memory for CRT
NC 13 NC 14 W
15 32 31 30 29 28 27 26 25 24 23
NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS(0V)
PIN DESCRIPTION
Pin name A0~A8 DQ1~DQ16 RAS LCAS UCAS W OE VCC VSS 1 Function Address inputs Data inputs / outputs Row address strobe input Lower byte control column address strobe input Upper byte control column address strobe input Write control input Output enable input Power supply (+5V) Ground (0V)
RAS 16 NC 17 A0 18 A1 19 A2 20 A3 21 (5V)VCC 22
Outline 44P3W-R (400mil TSOP Nomal Bend)
NC: NO CONNECTION
MITSUBISHI LSIs
M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
FUNCTION
In addition to Hyper page mode, normal read, write and readmodify-write operations the M5M44265CJ, TP provides a number of of other functions, e.g., RAS-only refresh and delayed-write. The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write RAS only refresh Hidden refresh
CAS before RAS (Extended*) refresh
Inputs RAS ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT NAC LCAS ACT NAC ACT ACT NAC ACT NAC ACT ACT ACT DNC UCAS NAC ACT ACT NAC ACT ACT NAC ACT ACT ACT DNC W NAC NAC NAC ACT ACT ACT DNC NAC DNC DNC DNC OE ACT ACT ACT NAC NAC NAC DNC ACT DNC DNC DNC DQ1~DQ8 DOUT OPN DOUT DIN DNC DIN OPN DOUT OPN OPN OPN
Input/Output DQ9~DQ16 OPN DOUT DOUT DNC DIN DIN OPN DOUT OPN OPN OPN
Self refresh* Stand-by
Note : ACT : active, NAC : nonactive, DNC : don' t care, OPN : open
BLOCK DIAGRAM
ROW ADDRESS STROBE INPUT RAS LOWER BYTE CONTROL COLUMN ADDRESS LCAS STROBE INPUT UPPER BYTE CONTROL UCAS COLUMN ADDRESS STROBE INPUT WRITE CONTROL INPUT
VCC (5V)
CLOCK GENERATOR CIRCUIT
VSS (0V) LOWER UPPER
(8)LOWER DATA IN BUFFER
W
(8)LOWER DATA OUT BUFFER
DQ1 DQ2 LOWER DATA INPUTS / OUTPUTS DQ8 VCC (5V) VSS (0V)
A0~A8 COLUMN DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8
(8) UPPER DATA IN BUFFER
ADDRESS INPUTS
ROW & COLUMN ADDRESS BUFFER
SENSE REFRESH AMPLIFIER & I /O CONTROL
(8)UPPER DATA OUT BUFFER
DQ9 DQ10 UPPER DATA INPUTS / OUTPUTS DQ16
A0~ A8
ROW DECO DER
MEMORY CELL (4194304 BITS)
VCC (5V) VSS (0V)
OE
OUTPUT ENABLE INPUT
2
MITSUBISHI LSIs
M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
ABSOLUTE .