M58LW128A

M58LW128A M58LW128B 128 Mbit (8Mb x16 or 4Mb x32, Uniform Block, Burst) 3V Supply Flash Memories PRELIMINARY DATA FEATURES SUMMARY s WIDE DATA BUS for HIGH BANDWIDTH – M58LW128A: x16 – M58LW128B: x16/x32 s Figure 1. Packages SUPPLY VOLTAGE – VDD = 2.7 to 3.6V core supply voltage for Program, Erase and Read operations – VDDQ = 1.8 to VDD for I/O Buffers s SYNCHRONOUS/ASYNCHRONOUS READ – Synchronous Burst read – Pipelined Synchronous Burst Read – Asynchronous Random Read – Asynchronous Address Latch Controlled Read – Page Read TSOP56 (N) 14 x 20mm TBGA TBGA64 (ZA) 10 x 13mm s ACCESS TIME – Synchronous Burst Read up to 66MHz – Asynchronous Page Mode Read 150/25ns – Random Read 150ns TBGA s PROGRAMMING TIME – 16 Word or 8 Double-Word Write Buffer – 12µs Word effective programming time TBGA80 (ZA) 10 x 13mm s s s s s s 128 UNIFORM 64 KWord MEMORY BLOCKS BLOCK PROTECTION/ UNPROTECTION PROGRAM and ERASE SUSPEND OTP SECURITY AREA COMMON FLASH INTERFACE 100,000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE – Manufacturer Code: 0020h – Device Code M58LW128A: 8818h – Device Code M58LW128B: 8819h s February 2003 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/65 M58LW128A, M58LW128B TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic Diagram . . . . ....