Document
M29F080A
8 Mbit (1Mb x8, Uniform Block) Single Supply Flash Memory
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SINGLE 5V±10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS ACCESS TIME: 70ns PROGRAMMING TIME – 8µs by Byte typical
44
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16 UNIFORM 64 Kbyte MEMORY BLOCKS PROGRAM/ERASE CONTROLLER – Embedded Byte Program algorithm – Embedded Multi-Block/Chip Erase algorithm – Status Register Polling and Toggle Bits – Ready/Busy Output Pin
TSOP40 (N) 10 x 20mm SO44 (M)
1
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ERASE SUSPEND and RESUME MODES – Read and Program another Block during Erase Suspend Figure 1. Logic Diagram
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TEMPORARY BLOCK UNPROTECTION MODE LOW POWER CONSUMPTION – Standby and Automatic Standby 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION – Defectivity below 1 ppm/year ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: F1h
A0-A19 W E G RP M29F080A RB VCC
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20
8 DQ0-DQ7
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VSS
AI00501C
April 2000
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M29F080A
Figure 2. TSOP Connections Figure 3. SO Connections
NC RP A11 A10 A9 A8 A7 A6 A5 A4 NC NC A3 A2 A1 A0 DQ0 DQ1 DQ2 DQ3 VSS VSS 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 34 M29F080A 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23
AI00521B
A19 A18 A17 A16 A15 A14 A13 A12 E VCC NC RP A11 A10 A9 A8 A7 A6 A5 A4
1
40
10 11
M29F080A
31 30
20
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AI00520B
NC NC W G RB DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3
VCC E A12 A13 A14 A15 A16 A17 A18 A19 NC NC NC NC W G RB DQ7 DQ6 DQ5 DQ4 VCC
Table 1. Signal Names
A0-A19 DQ0-DQ7 E G W RP RB VCC VSS NC Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Ready/Busy Output Supply Voltage Ground Not Connected Internally
SUMMARY DESCRIPTION The M29F080A is an 8 Mbit (1Mb x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed us-
ing a single 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Blocks can be protected in groups to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in a TSOP40 (10 x 20mm) and SO44 packages and it is supplied with all the bits erased (set to ’1’).
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M29F080A
Table 2. Absolute Maximum Rati.