MC12009

Order this document by MC12009/D Dual Modulus Prescaler These devices are two–modulus prescalers which will divide by 5 and 6, 8 and 9, and 10 and 11, respectively. A MECL–to–MTTL translator is provided to interface directly with the MC12014 Counter Control Logic. In addition, there is a buffered clock input and MECL bias voltage source. MC12009 480 MHz ( 5/6), MC12011 550 MHz ( 8/9), MC12013 550 MHz ( 10/11) MECL to MTTL Translator on Chip MC12009 MC12011 MC12013 MECL PLL COMPONENTS DUAL MODULUS PRESCALER SEMICONDUCTOR TECHNICAL DATA B B B MECL and MTTL Enable Inputs 5.0 or –5.2 V Operation* Buffered Clock Input — Series Input RC Typ, 20 Ohms and 4 pF VBB Reference Voltage 310 Milliwatts (Typ) * When using a 5.0 V supply, apply 5.0 V to Pin 1 (VCCO ), Pin 6 (MTTL V CC ), Pin 16 (V CC ), and ground Pin 8 (V EE ). When using –5.2 V supply, ground Pin 1 (V CCO ), Pin 6 (MTTL V CC ), and Pin 16 (V CC ) and apply –5.2 V to Pin 8 (V EE ). If the translator is not required, Pin 6 may be left open to conserve dc power drain. 16 1 P SUFFIX PLASTIC PACKAGE CASE 648 PIN CONNECTIONS VCCO Q 1 2 3 4 5 6 7 8 (Top View) 16 VCC 15 Clock 14 VBB 13 E1 MECL 12 E2 MECL 11 E3 MECL 10 E4 MECL 9 E5 MECL MAXIMUM RATINGS Characteristic Symbol Rating Unit Q (–) (+) MTTL VCC –8.0 0 to VEE Vdc Vdc mAdc MTTL Output VEE (Ratings above which device life may be impaired) Power Supply Voltage (VCC = 0) Input Voltage (VCC = 0) Output Source Current Continuous Surge Storage Temperatu...