MC10LVELT23D

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview Dual Differential LVPECL to TTL Translator The MC100LVELT23 is a dual differential LVPECL to TTL translator. Because LVPECL (Positive ECL) levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the LVELT23 makes it ideal for applications which require the translation of a clock and a data signal. The LVELT23 is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external VBB reference, the LVELT23 does not require both ECL standard versions. The LVPECL inputs are differential; there is no specified difference between the differential input 10H and 100K standards. Therefore, the MC100LVELT23 can accept any standard differential LVPECL input referenced from a VCC of 3.3V. MC100LVELT23 2.0ns Typical Propagation Delay Differential LVPECL Inputs Small Outline SOIC Package 24mA TTL Outputs Flow Through Pinouts ESD Performance: Human Body Model 1200V; Machine Model 150V D SUFFIX 8–LEAD PLASTIC SOIC PACKAGE CASE 751–05 Note: 1) Pulling the output higher than VCC is not recommended. Doing so causes excessive leakage and possible latchup leading to reliability risk. PIN DESCRIPTION D0 1 8 VCC PIN FUNCTION TTL Outputs Diff LVPECL Inputs +3.3V Supply Ground Qn Dn VCC GND D0 2 LVPECL TTL 7 Q0 D1 3 6 Q1 D1 4 5 GND Figure 1. 8–Lead Pinout and Logic Diagram This document contains information on a product under d...