MC10161

MC10161 Binary to 1-8 Decoder (Low) The MC10161 is designed to decode a three bit input word to a one of eight line output. The selected output will be low while all other outputs will be high. The enable inputs, when either or both are high, force all outputs high. The MC10161 is a true parallel decoder. No series gating is used internally, eliminating unequal delay times found in other decoders. This design provides the identical 4 ns delay from any address or enable input to any output. A complete mux/demux operation on 16 bits for data distribution is illustrated in Figure 1. This system, using the MC10136 control counters, has the capability of incrementing, decrementing or holding data channels. When both S0 and S1 are low, the index counters reset, thus initializing both the mux and demux units. The four binary outputs of the counter are buffered by the MC10161s to send twisted–pair select data to the multiplexer/demultiplexer to units. PD = 315 mW typ/pkg (No Load) tpd = 4.0 ns typ tr, tf = 2.0 ns typ (20%–80%) LOGIC DIAGRAM E0Ą2 E1Ą15 www.DataSheet4U.com 6ĄQ0 http://onsemi.com MARKING DIAGRAMS 16 CDIP–16 L SUFFIX CASE 620 1 16 PDIP–16 P SUFFIX CASE 648 1 1 PLCC–20 FN SUFFIX CASE 775 10161 AWLYYWW MC10161P AWLYYWW MC10161L AWLYYWW 5ĄQ1 4ĄQ2 3ĄQ3 AĄ7 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week DIP PIN ASSIGNMENT 13ĄQ4 BĄ9 12ĄQ5 11ĄQ6 CĄ14 10ĄQ7 VCC1 E0 Q3 Q2 Q1 Q0 A VEE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 E1 C Q4 Q5 VCC1 = PIN...