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MC10131 Dual Type D Master-Slave Flip-Flop
The MC10131 is a dual master–slave type D flip–flop. Asynchronous Set (S) and Reset (R) override Clock (CC) and Clock Enable (CE) inputs. Each flip–flop may be clocked separately by holding the common clock in the low state and using the enable inputs for the clocking function. If the common clock is to be used to clock the flip–flop, the Clock Enable inputs must be in the low state. In this case, the enable inputs perform the function of controlling the common clock. The output states of the flip–flop change on the positive transition of the clock. A change in the information present at the data (D) input will not affect the output information at any other time due to master slave construction. • PD = 235 mW typ/pkg (No Load) • FTog = 160 MHz typ • tpd = 3.0 ns typ • tr, tf = 2.5 ns typ (20%–80%)
DIP PIN ASSIGNMENT
VCC1 Q1 Q1 R1 S1 CE1 D1 VEE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 Q2 Q2 R2 S2 CE2 D2 CC C L H H
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http://onsemi.com MARKING DIAGRAMS
16 CDIP–16 L SUFFIX CASE 620 1 16 PDIP–16 P SUFFIX CASE 648 1 1 PLCC–20 FN SUFFIX CASE 775 10131 AWLYYWW MC10131P AWLYYWW MC10131L AWLYYWW
A WL YY WW
= Assembly Location = Wafer Lot = Year = Work Week
CLOCKED TRUTH TABLE
D X L H Qn+1 Qn L H
Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D).
LOGIC DIAGRAM
S1 5 D1 7 CE1 6 Q1 R1 4 CC 9 R2 13 Q2 CE2 11 D2 10 S2 12 Q2 14 15 3 Q1 2
C = CE + CC.A clock H is a clock transition from a low to a high state.
R–S TRUTH TABLE
R L L H H
N.D. = Not Defined
S L H L H
Qn+1 Qn H L N.D.
ORDERING INFORMATION
Device MC10131L Package CDIP–16 PDIP–16 PLCC–20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail
VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8
© Semiconductor Components Industries, LLC, 2002
MC10131P MC10131FN
1
January, 2002 – Rev. 7
Publication Order Number: MC10131/D
MC10131
ELECTRICAL CHARACTERISTICS
Test Limits Pin Under Test 8 4 5 6 7 9 4, 5* 6, 7, 9* 2 2[ 2 3[ 2 2[ 2 3[ 0.5 0.5 –1.060 –1.060 –1.890 –1.890 –1.080 –1.080 –1.655 –1.655 –0.890 –0.890 –1.675 –1.675 –30°C Min Max 62 525 525 350 390 425 0.5 0.5 –0.960 –0.960 –1.850 –1.850 –0.980 –0.980 –1.630 –1.630 –0.810 –0.810 –1.650 –1.650 Min +25°C Typ 45 Max 56 330 330 220 245 265 0.3 0.3 –0.890 –0.890 –1.825 –1.825 –0.910 –0.910 –1.595 –1.595 –0.700 –0.700 –1.615 –1.615 Min +85°C Max 62 330 330 220 245 265 Unit mAdc µAdc
Characteristic Power Supply Drain Current Input Current
Symbol IE IinH
IinL Output Voltage Output Voltage Threshold Voltage Threshold Voltage Logic 1 Logic 0 Logic 1 Logic 0 VOH VOL VOHA VOLA
µAdc Vdc Vdc Vdc Vdc ns
Switching Times (50Ω Load) Clock Input Propagation Delay t9+2– t9+2+ t6+2+ t6+2– t2+ t2– 2 2 2 2 2 2 1.7 1.7 1.7 1.7 1.0 1.0 4.6 4.6 4.6 4.6 4.6 4.6 1.8 1.8 1.8 1.8 1.1 1.1 3.0 3.0 3.0 3.0 2.5 2.5 4.5 4.5 4.5 4.5 4.5 4.5 1.8 1.8 1.8 1.8 1.1 1.1 5.0 5.0 5.0 5.0 4.9 4.9
Rise Time Fall Time .