MC10107

MC10107 Triple 2-Input Exclusive OR/ Exclusive NOR Gate The MC10107 is a triple–2 input exclusive OR/NOR gate. PD = 40 mW typ/gate (No Load) tpd = 2.8 ns typ tr, tf = 2.5 ns typ (20%–80%) LOGIC DIAGRAM 4 5 9 7 14 15 3 = (4 5) + (4 5) 2 = (4 5) + (4 5) VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 2 3 11 10 12 13 PDIP–16 P SUFFIX CASE 648 1 1 PLCC–20 FN SUFFIX CASE 775 10107 AWLYYWW CDIP–16 L SUFFIX CASE 620 1 16 MC10107P AWLYYWW http://onsemi.com MARKING DIAGRAMS 16 MC10107L AWLYYWW DIP PIN ASSIGNMENT VCC1 AOUT AOUT AIN AIN *NC BIN VEE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 CIN CIN COUT COUT BOUT BOUT BIN www.DataSheet4U.com A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device MC10107L MC10107P MC10107FN Package CDIP–16 PDIP–16 PLCC–20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail *NC = No Connection Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). © Semiconductor Components Industries, LLC, 2002 1 January, 2002 – Rev. 7 Publication Order Number: MC10107/D MC10107 ELECTRICAL CHARACTERISTICS Test Limits Pin Under Test 8 4, 9, 14 5, 7, 15 * 2 2 3 3 2 2 3 3 2 2 3 3 2 2 3 3 0.5 –1.060 –1.060 –1.060 –1.060 –1.890 –1.890 –1.890 –1.890 –1.080 –1.080 –1.080 –1.080 –1.655 –1.655 –1.655 –1.655 Min t++ t+ – t–+ t– – t++ t+ – t–+ t– – Rise Time Fall Time (20 to 80%) (20 to 80%) t+ t– Inputs 4,9 or 14 to eith...