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MC10106 Dataheets PDF



Part Number MC10106
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description Triple 4-3-3-Input NOR Gate
Datasheet MC10106 DatasheetMC10106 Datasheet (PDF)

MC10106 Triple 4-3-3-Input NOR Gate • • • The MC10106 is a triple 4–3–3 input NOR gate. PD = 30 mW typ/gate (No Load) tpd = 2.0 ns typ tr, tf = 2.0 ns typ (20%–80%) LOGIC DIAGRAM 4 5 6 7 9 10 11 12 13 14 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 www.DataSheet4U.com http://onsemi.com MARKING DIAGRAMS 16 3 CDIP–16 L SUFFIX CASE 620 1 MC10106L AWLYYWW 2 PDIP–16 P SUFFIX CASE 648 16 MC10106P AWLYYWW 1 1 PLCC–20 FN SUFFIX CASE 775 10106 AWLYYWW 15 DIP PIN ASSIGNMENT VCC1 BOUT AOUT AIN AIN AIN AI.

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MC10106 Triple 4-3-3-Input NOR Gate • • • The MC10106 is a triple 4–3–3 input NOR gate. PD = 30 mW typ/gate (No Load) tpd = 2.0 ns typ tr, tf = 2.0 ns typ (20%–80%) LOGIC DIAGRAM 4 5 6 7 9 10 11 12 13 14 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 www.DataSheet4U.com http://onsemi.com MARKING DIAGRAMS 16 3 CDIP–16 L SUFFIX CASE 620 1 MC10106L AWLYYWW 2 PDIP–16 P SUFFIX CASE 648 16 MC10106P AWLYYWW 1 1 PLCC–20 FN SUFFIX CASE 775 10106 AWLYYWW 15 DIP PIN ASSIGNMENT VCC1 BOUT AOUT AIN AIN AIN AIN VEE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 COUT CIN CIN CIN BIN BIN BIN A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device MC10106L MC10106P MC10106FN Package CDIP–16 PDIP–16 PLCC–20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). © Semiconductor Components Industries, LLC, 2002 1 January, 2002 – Rev. 7 Publication Order Number: MC10106/D MC10106 ELECTRICAL CHARACTERISTICS Test Limits Pin Under Test 8 4 4 3 2 3 2 3 2 3 2 0.5 –1.060 –1.060 –1.890 –1.890 –1.080 –1.080 –1.655 –1.655 –0.890 –0.890 –1.675 –1.675 –30°C Min Max 23 425 0.5 –0.960 –0.960 –1.850 –1.850 –0.980 –0.980 –1.630 –1.630 –0.810 –0.810 –1.650 –1.650 Min +25°C Typ 17 Max 21 265 0.3 –0.890 –0.890 –1.825 –1.825 –0.910 –0.910 –1.595 –1.595 –0.700 –0.700 –1.615 –1.615 Min +85°C Max 23 265 Unit mAdc µAdc µAdc Vdc Vdc Vdc Vdc ns t4+3– t4–3+ t3+ t3– 3 3 3 3 1.0 1.0 1.1 1.1 3.1 3.1 3.6 3.6 1.0 1.0 1.1 1.1 2.0 2.0 2.0 2.0 2.9 2.9 3.3 3.3 1.0 1.0 1.1 1.1 3.3 3.3 3.7 3.7 Characteristic Power Supply Drain Current Input Current Symbol IE IinH IinL Output Voltage Output Voltage Threshold Voltage Threshold Voltage Logic 1 Logic 0 Logic 1 Logic 0 VOH VOL VOHA VOLA Switching Times (50Ω Load) Propagation Delay Rise Time Fall Time (20 to 80%) (20 to 80%) ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) @ Test Temperature –30°C +25°C +85°C Pin Under Test 8 4 4 3 2 3 2 3 2 3 2 4 9 Pulse In t4+3– t4–3+ (20 to 80%) (20 to 80%) t3+ t3– 3 3 3 3 4 4 4 4 Pulse Out 3 3 3 3 4 9 4 9 4 4 VIHmax –0.890 –0.810 –0.700 VILmin –1.890 –1.850 –1.825 VIHAmin –1.205 –1.105 –1.035 VILAmax –1.500 –1.475 –1.440 VEE –5.2 –5.2 –5.2 (VCC) Gnd 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 +2.0 V 1, 16 1, 16 1, 16 1, 16 TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax VEE 8 8 8 8 8 8 8 8 8 8 8 –3.2 V 8 8 8 8 Characteristic Power Supply Drain Current Input Current Symbol IE IinH IinL Output Voltage Output Voltage Threshold Voltage Threshold Voltage Switching Times Propagation Delay Rise Time Fall Time Logic 1 Logic 0 Logic 1 Logic 0 (50Ω Load) VOH VOL VOHA VOLA Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. http://onsemi.com 2 MC10106 PACKAGE DIMENSIONS PLCC–20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775–02 ISSUE C B –N– Y BRK D –L– –M– W D X V A Z R 0.007 (0.180) 0.007 (0.180) M 0.007 (0.180) U M T L-M M S N S S 0.007 (0.180) T L-M N S Z 20 1 G1 0.010 (0.250) S T L-M S N S VIEW D–D T L-M T L-M S N N S H 0.007 (0.180) M T L-M S N S M S S K1 K C E 0.004 (0.100) G G1 0.010 (0.250) S T L-M J –T– SEATING PLANE F VIEW S NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). 0.007 (0.180) M T L-M S N S VIEW S S N S DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --0.025 --0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --0.020 2_ 10 _ 0.310 0.330 0.040 --- MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2..


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