Triple 2-3-2-Input OR/NOR Gate
MC10105 Triple 2-3-2-Input OR/NOR Gate
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The MC10105 is a triple 2–3–2 input OR/NOR gate. PD = 30 mW typ/gate (No Lo...
Description
MC10105 Triple 2-3-2-Input OR/NOR Gate
The MC10105 is a triple 2–3–2 input OR/NOR gate. PD = 30 mW typ/gate (No Load) tpd = 2.0 ns typ tr, tf = 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
4 5 9 10 11 13 12 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 3 2 6 7 14 15 PDIP–16 P SUFFIX CASE 648 1 1 PLCC–20 FN SUFFIX CASE 775 10105 AWLYYWW CDIP–16 L SUFFIX CASE 620 1 16 MC10105P AWLYYWW
http://onsemi.com MARKING DIAGRAMS
16 MC10105L AWLYYWW
DIP PIN ASSIGNMENT
VCC1 AOUT AOUT AIN AIN BOUT BOUT VEE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 COUT COUT CIN CIN BIN BIN BIN
www.DataSheet4U.com
A WL YY WW
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device MC10105L MC10105P MC10105FN Package CDIP–16 PDIP–16 PLCC–20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail
Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D).
© Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
Publication Order Number: MC10105/D
MC10105
ELECTRICAL CHARACTERISTICS
Test Limits Pin Under Test 8 4 4 3 2 3 2 3 2 3 2 0.5 –1.060 –1.060 –1.890 –1.890 –1.080 –1.080 –1.655 –1.655 –0.890 –0.890 –1.675 –1.675 –30°C Min Max 23 425 0.5 –0.960 –0.960 –1.850 –1.850 –0.980 –0.980 –1.630 –1.630 –0.810 –0.810 –1.650 –1.650 Min +25°C Typ 17 Max 21 265 0.3 –0.890 –0.890 –1.825 –1.825 –0.910 –0.910 –1.595 –1.595 –0.700 –0.700 –1.615 –1.615 Min +85°C Max 23 265 Unit mAdc µAd...
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