MC10104

MC10104 Quad 2-Input AND Gate The MC10104 is a quad 2–input AND gate. One of the gates has both AND/NAND outputs available. PD = 35 mW typ/gate (No Load) tpd = 2.7 ns typ tr, tf = 2.0 ns typ (20%–80%) LOGIC DIAGRAM 4 5 6 7 10 11 12 13 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 2 3 14 9 15 PDIP–16 P SUFFIX CASE 648 1 1 PLCC–20 FN SUFFIX CASE 775 10104 AWLYYWW CDIP–16 L SUFFIX CASE 620 1 16 MC10104P AWLYYWW http://onsemi.com MARKING DIAGRAMS 16 MC10104L AWLYYWW DIP PIN ASSIGNMENT VCC1 AOUT BOUT AIN AIN BIN BIN VEE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 DOUT COUT DIN DIN CIN CIN DOUT www.DataSheet4U.com A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device MC10104L MC10104P MC10104FN Package CDIP–16 PDIP–16 PLCC–20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). © Semiconductor Components Industries, LLC, 2002 1 January, 2002 – Rev. 7 Publication Order Number: MC10104/D MC10104 ELECTRICAL CHARACTERISTICS Test Limits Pin Under Test 8 12 13 12 15 9 15 9 9 9 15 15 9 9 15 15 0.5 –1.060 –1.060 –1.890 –1.890 –1.090 –1.090 –1.090 –1.090 –1.655 –1.655 –1.655 –1.655 –0.890 –0.890 –1.675 –1.675 –30°C Min Max 39 425 350 0.5 –0.960 –0.960 –1.850 –1.850 –0.980 –0.980 –0.980 –0.980 –1.630 –1.630 –1.630 –1.630 –0.810 –0.810 –1.650 –1.650 Min +25°C Typ Max 35 265 220 0.3 –0....