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MC100LVEL92 Dataheets PDF



Part Number MC100LVEL92
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description 5V Triple PECL Input to LVPECL Output Translator
Datasheet MC100LVEL92 DatasheetMC100LVEL92 Datasheet (PDF)

MC100LVEL92 5 V Triple PECL Input to LVPECL Output Translator Description The MC100LVEL92 is a triple PECL input to LVPECL output translator. The device receives standard PECL signals and translates them to differential LVPECL output signals. To accomplish the PECL to LVPECL level translation, the MC100LVEL92 requires three power rails. The VCC supply is to be connected to the standard 5 V PECL supply, the LVCC supply is to be connected to the 3.3 V LVPECL supply, and Ground is connected to the.

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MC100LVEL92 5 V Triple PECL Input to LVPECL Output Translator Description The MC100LVEL92 is a triple PECL input to LVPECL output translator. The device receives standard PECL signals and translates them to differential LVPECL output signals. To accomplish the PECL to LVPECL level translation, the MC100LVEL92 requires three power rails. The VCC supply is to be connected to the standard 5 V PECL supply, the LVCC supply is to be connected to the 3.3 V LVPECL supply, and Ground is connected to the system ground plane. Both the VCC and LVCC should be bypassed to ground with 0.01 mF capacitors. The PECL VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Features • 500 ps Propagation Delays • 5 V and 3.3 V Supplies Required • ESD Protection: Human Body Model; > 2 kV, Machine Model; > 200 V • The 100 Series Contains Temperature Compensation • LVPECL Operating Range: LVCC = 3.0 V to 3.8 V • PECL Operating Range: VCC = 4.5 V to 5.5 V • Internal Input Pulldown Resistors • Q Output will Default LOW with Inputs Open or < GND + 1.3 V • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • Moisture Sensitivity: Level 3 (Pb−Free) For Additional Information, see Application Note AND8003/D • Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index 28 to 34 • Transistor Count = 247 devices • These Devices are Pb-Free, Halogen Free and are RoHS Compliant www.onsemi.com SOIC−20 WB DW SUFFIX CASE 751D MARKING DIAGRAM* 20 100LVEL92 AWLYYWWG 1 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping† MC100LVEL92DWG SOIC−20 WB 38 Units/Tube (Pb-Free) MC100LVEL92DWR2G SOIC−20 WB 1000/Tape & Reel (Pb-Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2016 July, 2016 − Rev. 13 1 Publication Order Number: MC100LVEL92/D MC100LVEL92 VCC Q0 Q0 LVCC Q1 Q1 LVCC Q2 Q2 VCC 20 19 18 17 16 15 14 13 12 11 LVPECL LVPECL LVPECL PECL PECL PECL 1 2 3 4 5 6 7 8 9 10 VCC D0 D0 D1 D1 D2 D2 GND Table 1. PIN DESCRIPTION PIN Dn, Dn Qn, Qn PECL VBB LVCC VCC GND FUNCTION PECL Inputs LVPECL Outputs PECL Reference Voltage Output LVPECL Power Supply PECL Power Supply Common Ground Rail VBB PECL VBB PECL Warning: All VCC, LVCC, and GND pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Logic Diagram and Pinout: SO−20 WB (Top View) Table 2. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC LVCC VI Iout PECL Power Supply LVPECL Power Supply PECL Input Voltage Output Current GND = 0 V GND = 0 V GND = 0 V Continuous Surge VI ≤ VCC 8 to 0 8 to 0 6 to 0 50 100 V V V mA IBB PECL VBB Sink/Source TA Operating Temperature Range Tstg Storage Temperature Range qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm SOIC−20 WB ± 0.5 −40 to +85 −65 to +150 90 60 mA °C °C °C/W qJC Thermal Resistance (Junction-to-Case) Tsol Wave Solder (Pb-Free) Standard Board SOIC−20 WB < 2 to 3 sec @ 260°C 30 to 35 265 °C/W °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 2 MC100LVEL92 Table 3. PECL INPUT DC CHARACTERISTICS (VCC = 5.0 V; LVCC = 3.3 V; GND = 0 V Note 1)) −40°C 25°C Symbol Characteristic Min Typ Max Min Typ Max IVCC VIH VIL PECL VBB VIHCMR IIH IIL PECL Power Supply Current Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (DIfferential) (Note 2) Vpp < 500 mV Vpp ≥ 500 mV Input HIGH Current Input LOW Current D D 3835 3190 3.62 1.3 1.5 0.5 −600 12 4120 3515 3.74 3835 3190 3.62 4.8 1.2 4.8 1.4 150 0.5 −600 12 4120 3525 3.74 4.8 4.8 150 Min 3835 3190 3.62 1.2 1.4 0.5 −600 85°C Typ Max 12 4120 3525 3.74 4.8 4.8 150 Unit mA mV mV V V mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input paramet.


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