DSP Embedded Line and Port Interface Controller
Addendum
DS2.1, 2003-08-04 DELIC-LC/DELIC-PB DSP Embedded Line and Port Interface Controller PEB 20570/PEB 20571/PEF 205...
Description
Addendum
DS2.1, 2003-08-04 DELIC-LC/DELIC-PB DSP Embedded Line and Port Interface Controller PEB 20570/PEB 20571/PEF 20570/PEF 20571 Version 3.1
1
Addendum to “DELIC Clock System Synchronization”
The DELIC Clock System Synchronization is described in the DELIC-LC PEB 20570/ DELIC-PB PEB 20571 Data Sheet, independent of the version (2.1 .. 3.1). As an addendum to chapter “DELIC Clock System Synchronization” of the DELICLC/DELIC-PB Data Sheet the following describes the system behaviour when using the VIP PEB 20590 or PEB 20591 in LT-T mode, for example when synchronizing to the Central Office.
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Note: OCEM® and OakDSPCore® (OAK®) are registered trademarks of ParthusCeva, Inc..
Revision History: Previous Version: Major Changes: Addendum DS2, 2002-08-09
- Chapter 3: New PEF version of DELIC-LC/DELIC-PB is available - Chapter 4: DELIC Strap Option Configuration - Trademarks changed
Addendum
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2003-08-04
PEB 20570/PEF 20570 PEB 20571/PEF 20571
Addendum to “DELIC Clock System Synchronization” 1.1 Clocking the VIP in LT-T Mode by DELIC Layer 1 Clock
1 6 .3 8 4 M H z
DCXO
8 kH z PD MUX R EFCLK D ivid e r XCLK
1 6 .3 8 4 M H z PLL D ivid e r
D ivid e r 1 5 .3 6 M H z IN C L K OSC /1 0 C e n tra l O ffice R xP L L M ux VIP
DELIC L1_CLK
1 .5 3 6 M H z
REFCLK
DELIC _refclk1
Figure 1
Clocking the VIP by using DELIC Layer 1 Clock
When the Central Office is activated, its clock signal is retrieved by the RxPLL of the VIP and a 1.536 MHz reference sig...
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