LRS1331

LRS1331 Data Sheet FEATURES Flash Memory and SRAM Stacked Die Chip Scale Package 72-ball 8 mm × 11 mm CSP plastic package Power supply: 2.7 V to 3.6 V Operating temperature: -25°C to +85°C Flash Memory – Access time (MAX.): 90 ns – Operating current (MAX.) (The current for F-VCC pin and F-VCCW pin): – Read: 25 mA (tCYCLE = 200 ns) – Word write: 57 mA – Block erase: 42 mA – Standby current (the current for F-VCC pin): 15 µA (MAX. F-RP ≤ GND ± 0.2 V) – Optimized array blocking architecture – Two 4K-word boot blocks – Six 4K-word parameter blocks Stacked Chip 16M Flash Memory and 4M SRAM – Thirty-one 32K-word main blocks – Bottom boot location – Extended cycling capability – 100,000 block erase cycles – Enhanced automated suspend options – Word write suspend to read – Block erase suspend to word write – Block erase suspend to read SRAM – Access time (MAX.): 85 ns – Operating current: 45 mA (MAX.) – Standby current: 15 µA (MAX.) – Data retention current: 2 µA (MAX.) DESCRIPTION The LRS1331 is a combination memory organized as 1,048,576 × 16-bit flash memory and 262,144 × 16-bit static RAM in one package. PIN CONFIGURATION 72-BALL FBGA INDEX TOP VIEW 1 A B C D E F G H NC NC 2 NC 3 NC A16 4 A11 A8 5 A15 A10 T1 T2 6 A14 A9 7 A13 8 A12 9 F-GND 10 NC DQ7 DQ5 11 NC 12 NC DQ15 S-WE DQ14 DQ6 DQ4 F-WE F-RY/ BY S-A17 DQ13 T4 GND F-RP F-WP DQ12 S-CE2 S-VCC F-VCC T3 DQ9 DQ10 DQ2 DQ8 DQ0 DQ3 DQ1 F-VPP F-A19 DQ11 NC S-LB S-UB S-OE F-A18 NC NC F-A17 A5 A7 A4 ...