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LM9627 Color CMOS Image Sensor VGA 30 FPS
March 2001
LM9627 Color CMOS Image Sensor VGA 30 FPS
General Description
The LM9627 is a high performance, low power, third inch VGA CMOS Active Pixel Sensor capable of capturing color digital still or motion images and converting them to a digital data stream. In addition to the active pixel array, an on-chip 12 bit A/D convertor, fixed pattern noise elimination circuits and a video gain amplifier is provided. Furthermore, an integrated programmable smart timing and control circuit allows the user maximum flexibility in adjusting integration time, active window size, gain and frame rate. Various control, timing and power modes are also provided.
Applications
• • • • • • PC Camera Digital Still Camera Video Conferencing Security Cameras Toys Machine Vision
Key Specifications
• Array Format • Effective Image Area Total: 664H x 504V Active: 648H x 488V Total: 4.98mm x 3.78 mm Active: 4.86 mm x 3.66 mm 1/3“ 7.5µm x 7.5 µ m 8,10 & 12 Bit Digital 57dB 0.35% red green blue • Quantum Efficiency • Fill Factor • Color Mosaic • Package • Single Supply • Power Consumption • Operating Temp 14.5 kLSBs/lux.s 7.5 kLSBs/lux.s 5.1 kLSBs/lux.s 27% 47% (no micro lens) Bayer pattern 48 LCC 3.3 V 90 mW 0 to 50o C
Features
• • • • • • • • • • Supplied with micro lenses Video or snapshot operations Programmable pixel clock, inter-frame and inter-line delays. Programmable partial or full frame integration Programmable gain adjustment Horizontal & vertical sub-sampling (2:1 & 4:2) Windowing External snapshot trigger & event synchronisation signals Auto black level compensation Flexible digital video read-out supporting programmable: - polarity for synchronisation and pixel clock signals - leading edge adjustment for horizontal synchronization
• Optical Format • Pixel Size • Video Outputs • Dynamic Range • FPN • Sensitivity
• Programmable via 2 wire I2C compatible serial interface • Power on reset & power down mode
System Block Diagram
Storage lens LM9627 12bit digital image Digital Image Processor I2 C compatible event trigger snapshot
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LM9627
Overall Chip Block Diagram
Bad Pixel Detect & Correct Horizontal Shift Register Column CDS Black Level Compensation Digital Video Framer d[11:0] pclk hsync vsync
Row Address Decoder APS Array POR Reset Gen Row Address Gen Vertical Timing
AMP
12 Bit A/D
Horizontal Timing
Gain Control Register Bank I2C Compatible Serial I/F sda sclk sadr
Clock Gen
Controller (sequencer)
Master Timer
Power Control
mclk
extsync
snapshot irq pdwn Figure 1. Chip Block Diagram
Connection Diagram
vdd_od1 vss_od1 vdd_od3 vss_od3 extsync vdd_pix vsrvdd sadr
sda
6 sclk snapshot resetb pdwn vss_dig vdd_dig hsync vsync pclk mclk d0 NC 7 8 9 10 11 12 13 14 15 16 17 18
5
4
3
2
1
48 47 46 45 44 43 42 41 40 39 NC fine_i gnd fine_ctrl offset vdd_ana1 vss_ana1 vref_adc vss_ana2 vdd_ana2 vss_od2 vdd_od2
LM9627 48 PIN LCC
31 19 20 21 22 23 24 25 26 27 28 29 30 NC d1 d9 d2 d3 d4 d5 d6 d7 d8 d10 d11
Ordering Information
Temperature (0°C ≤ TA ≤ + 50°C) LM9627 CCEA NS Package LCC
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2
NC 38 37 36 35 34 33 32
irq
vrl
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LM9627
Typical Application Circuit
System Control Camera Control Serial Control Bus
16 mclk
9 resetb
10 pdwn
4 irq
8 snapshot
48 extsync
7 sclk
6 sda
5 sadr
3.3V analog
3.3V analog
37 vdd_ana1
0.1 µF
vdd_ana2 33 vss_ana2 34
3.3V digital 0.1µ F
36 vss_ana1
3.3V digital
47 vdd_od1
0.1 µF
vdd_od2 31 vss_od2 32
46 vss_od1
0.1µF
3.3V digital
3.3Vdigital
44 vdd_od3 45 vss_od3
vdd_dig
12
0.1 µF
0.1 µF
vss_dig 11
3.3V analog
3 vdd_pix 2 vrl
LM9627
vsrvdd 1
1.0 µF
0.1 µF
3.3V analog
vdd_ana
vdd_ana
1.5k Ω
35
820Ω 0.1µF
vref_adc
fine_i 41 fine_ctrl 39
1N4148
22k Ω 1%
2N3904
10k Ω 1%
18 19 42 43
NC NC NC NC hsync vsync pclk d10 d11 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
1.2k Ω 1%
offset 38
4.7 µ F 470 Ω 1%
gnd 40
13 14 15
30 29 28 27 26 25 24 23 22 21 20 17
Digital Video Bus Figure 2. Typical Application Diagram
Scan Read Out Direction
pin 1 (0,0) vertical scan (0,0) digital out
(0,0) horizontal scan lens CMOS Image Sensor
Figure 3. Scan directions and position of origin in imaging system
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LM9627
Pin Descriptions
Pin 1 2 3 4 Name vsrvdd vrl vdd_pix irq I/O I0 I I O Typ P A P D Description Analog bidirectional, it should be connect to ground via a 1.0µ f capacitor. This pin is the internal charge pump voltage source. Anti blooming pin. This pin is normally tied to ground. 3.3 volt supply for the pixel array. Digital output, the interrupt request pin. This pin generates interrupts during snapshot mode. Digital input with pull down resistor. This pin is used to program different slave addresses for the sensor in an I2 C compatible system. I2 C compatible serial interface data bus. The output stage of this pin has an open drain driver. I2 C compatible serial interface clock. Di.