Document
PDSP16510 PDSP16510A
Stand Alone FFT Processor
Supersedes version in December 1993 Digital Video & DSP IC Handbook, HB3923-1 DS3475 - 4.4 May 1996
The PDSP16510 performs Forward or Inverse Fast Fourier Transforms on complex or real data sets containing up to 1024 points. Data and coefficients are each represented by 16 bits, with block floating point arithmetic for increased dynamic range. An internal RAM is provided which can hold up to 1024 complex data points. This removes the memory transfer bottleneck, inherent in building block solutions. Its organisation allows the PDSP16510 to simultaneously input new data, transform data stored in the RAM, and to output previous results. No external buffering is needed for transforms containing up to 256 points, and the PDSP16510 can be directly connected to an A/D converter to perform continuous transforms. The user can choose to overlap data blocks by either 0%, 50%, or 75%. Inputs and outputs are synchronous to the 40MHz system clock used for internal operations. A 1024 point complex transform can be completed in some 98µs, which is equivalent to throughput rates of 450 million operations per second. Multiple devices can be connected in parallel in order to increase the sampling rate up to the 40MHz system clock. Six devices are needed to give the maximum performance with 1024 point transforms. Either a Hamming or a Blackman-Harris window operator can be internally applied to the incoming real or complex data. The latter gives 67dB side lobe attenuation. The operator values are calculated internally and do not require an external ROM nor do they incur any time penalty. The device outputs the real and imaginary components of the frequency bins. These can be directly connected to the PDSP16330 in order to produce magnitude and phase values from the complex data.
DATA INPUT
3 TERM WINDOW OPERATOR
COEFFICIENT ROM
WORKSPACE RAM
WORKSPACE RAM
FOUR DATA PATHS
OUTPUT BUFFER
RESULT OUPUT
Fig. 1. Block Diagram
FEATURES
Completely self contained FFT Processor Internal RAM supports up to1024 complex points 16 bit data and coefficients plus block floating point for increased dynamic range 450 MIP operation gives 98 microsecond transformation times for 1024 points
ASSOCIATED PRODUCTS
PDSP16540 Bucket Buffer PDSP16330 Pythagoras Processor. PDSP16256 Programmable FIR Filter. PDSP16350 I/Q Splitter / NCO
Up to 40MHz sampling rates with multiple devices. Internal window operator gives 67dB side lobe attenuation and needs no external ROM. 84 pin PGA or 132 surface mount package
SAMPLE CLOCK
CONFIGURATION WORD DIS AUX15:0
GND INEN DOS R15:0 X CLK PHASE
ANALOG INPUT
PDSP16510 A/D
D15:0 I15:0 Y DEF DEN DAV S3:0 GND RESET
PDSP16330
MAGNITUDE
SCALE VALUE AVAILABLE
1
Fig. 2. Typical 256 Point Real Only System Performing Continuous Transforms
PDSP16510
N
D9
D10
D12
D14
DIS
VDD
DAV
GND
AUX0
AUX2
AUX4
AUX6
AUX7
M
D8
D11
D13
D15
DEF
INEN
SCLK
AUX1
AUX3
AUX5
AUX8
L
D6
D7
AUX9
AUX10
K
D4
D5
AUX11
AUX12
J
D2
D3
AUX13
AUX14
H
GND
D1
AUX15
GND
G
D0
LFLG
DEN
I15
F
VDD
R0
I14
VDD
E
R1
R2
I12
I13
D
R3
R4
I10
I11
C
R5
R6
I8
I9
B
R7
R10
R12
R14
S0
DOS
S2
I0
I2
I4
I7
A
R8
R9
R11
R13
R15
VDD
S1
GND
S3
I1
I3
I5
I6
1
2
3
4
5
6
7
8
9
10
11
12
13
Pin Out for 84 PGA Package (AC84) - bottom view
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 FUNC VDD GND I7 I8 I9 I10 VDD I11 GND I12 VDD I13 GND I14 VDD I15 GND DEN AUX15 GND AUX14 GND PIN 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 FUNC AUX13 VDD AUX12 GND AUX11 VDD GND AUX10 AUX9 AUX8 AUX7 VDD AUX6 VDD AUX5 GND AUX4 AUX3 AUX2 VDD AUX1 AUX0 PIN 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 FUNC GND VDD SCLK GND GND DAV GND INEN VDD DEF GND DIS VDD D15 D14 GND D13 D12 D11 D10 VDD D9 PIN 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 FUNC D8 D7 D6 D5 GND VDD D4 GND D3 VDD D2 GND D1 VDD D0 LFLG GND R0 GND R1 VDD R2 PIN 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 FUNC GND R3 VDD R4 GND R5 R6 R7 R8 GND VDD R9 VDD R10 R11 R12 R13 GND R14 R15 DISAB S0 PIN 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 FUNC GND S1 GND DOS DOS VDD S2 GND S3 GND VDD I0 I1 GND I2 I3 I4 GND VDD I5 I6 VDD
2
Pin Out for 132 Leaded Chip Carrier (GC132)
PDSP16510
SIGNAL D15:0 AUX15:0
TYPE I I
DESCRIPTION Data input during real only mode. The real component in complex data mode. When DEF is active AUX15:0 are used to define the operating mode as defined in Table 3. When DEF is in-active AUX15:0 either provide the 16 bit imaginary component of complex input data, or a second set of real only inputs. These pins output the real component of the transformed data when DAV and DEN are active. Otherwise they are high impedance. These pins output the imaginary component of the transformed data when DAV and DEN are ac.