OCTAL D-TYPE FLIP FLOP
M54/74HC564 M54/74HC574
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HC564 INVERTING - HC574 NON INVERTING
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Description
M54/74HC564 M54/74HC574
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HC564 INVERTING - HC574 NON INVERTING
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HIGH SPEED fMAX = 62 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28% VCC (MIN) OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOL = IOH= 6 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS564/574
B1R (Plastic Package)
F1R (Ceramic Package)
M1R (Micro Package)
C1R (Chip Carrier)
ORDER CODES : M54HCXXXF1R M74HCXXXM1R M74HCXXXB1R M74HCXXXC1R
DESCRIPTION The M54/74HC564 and M54HC574 are high speed CMOS OCTAL D-TYPE FLIP FLOP WITH 3-STATE 2 OUTPUTS fabricated with in silicon gate C MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power comsuption. These8-bit D-type flip-flops are controlled by a clock input (CK) and an ouput enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs (HC574) or their complements (HC564). While the OE input is low, the eight outputs will be in a normal logic state (high or low logic level), and while high level, the outputs will be in a high impedPIN CONNECTION (top view)
ance state. The output control does not affect the internal operation of flip-flops. That is, the old data can be retained or the new data can be ente...
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