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M54HC323 Dataheets PDF



Part Number M54HC323
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description 8-BIT PIPO SHIFT REGISTER
Datasheet M54HC323 DatasheetM54HC323 Datasheet (PDF)

M54/74HC299 M54/74HC323 HC299 8 BIT PIPO SHIFT REGISTER WITHASYNCHRONOUS CLEAR HC323 8 BIT PIPO SHIFT REGISTER WITH SYNCHRONOUS CLEAR . . . . . . . . HIGH SPEED fMAX = 42 MHz (TYP.) AT VCC = 5V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS FOR QA’ TO QH’ 15 LSTTL LOADS FOR QA TO QH SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 6 mA (MIN.) FOR Q A, TO QH, IOH = IOL = 4 mA (MIN.) FOR Q A, TO QH BALANC.

  M54HC323   M54HC323


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M54/74HC299 M54/74HC323 HC299 8 BIT PIPO SHIFT REGISTER WITHASYNCHRONOUS CLEAR HC323 8 BIT PIPO SHIFT REGISTER WITH SYNCHRONOUS CLEAR . . . . . . . . HIGH SPEED fMAX = 42 MHz (TYP.) AT VCC = 5V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS FOR QA’ TO QH’ 15 LSTTL LOADS FOR QA TO QH SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 6 mA (MIN.) FOR Q A, TO QH, IOH = IOL = 4 mA (MIN.) FOR Q A, TO QH BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS299 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HCXXXF1R M74HCXXXM1R M74HCXXXB1R M74HCXXXC1R PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC299/323 are high speed CMOS 8BIT PIPO SHIFT REGISTERS (3-STATE) fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power consumption. These devices have four modes (HOLD, SHIFT LEFT, SHIFT RIGHT and LOAD DATA). Each mode is chosen by two function select inputs (S0, S1). When one or both enable inputs, (G1, G2) are high, the eight input/output terminals are in the highimpedance state ; however sequential operation or clearing of the register is not affected. Clear function on the HC299 is asynchronous to CLOCK, while the HC323 is cleared synchronous to clock. All inputs are equipped with protection circuits against static discharge and transient excess voltage. October 1993 NC = No Internal Connection 1/15 M54/M74HC299/323 INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE INPUTS MODE CLEAR L L L H H H H H H FUNCTION SELECTED S1 Z CLEAR HOLD SHIFT RIGHT SHIFT LEFT LOAD H L X L L L H H H S0 H X L L H H L L H OUTPUT CONTROL G1 * X L L L L L L L X G2 * X L L L L L L L X CLOCK (299) X X X X (323) INPUTS/OUTPUTS SERIAL SL X X X X X X H L X SR X X X X H L X X X Z L L QA0 H L QBn QBn a Z L L QH0 QGn QGn H L h L L L QA0 H L QBn QBn a L L L QH0 QGn QGn H L h A/QA H/QH OUTPUTS QA’ QH’ * When one or both output controls are high, the eight, input/output terminals are in thehigh impedance state: however sequential operation or clearing of the register is not affected. Z : HIGH IMPEDANCE Qn0 : THE LEVEL OF An BEFORE THE INDICATED STEADY STATE INPUT CONDITIONS WERE ESTABLISHED. Qnn : THE LEVEL ON Qn BEFORE THE MOST RECENT ACTIVE TRANSITION INDICATED BY OR a, h : THE LEVEL OF THE STEADY STATE INPUTS A, H, RESPECTIVELY. X : DON’T CARE 2/15 M54/M74HC299/323 LOGIC DIAGRAM (HC299) 3/15 M54/M74HC299/323 LOGIC DIAGRAM (HC323) 4/15 M54/M74HC299/323 TIMING CHART IEC LOGIC SYMBOLS HC299 HC299 5/15 M54/M74HC299/323 PIN DESCRIPTION PIN No 1, 19 2, 3 7, 13, 6, 14, 5, 15, 4, 16 8, 17 9 11 12 18 10 20 SYMBOL S0, S1 G1, G2 A/QA to H/QH QA’ to QH’ CLEAR SR CLOCK SL GND VCC NAME AND FUNCTION Mode Select Inputs 3 State Output Enable Inputs (Active LOW) Parallel Data Inputs or 3 State Parallel Outputs (Bus Driver) Serial Outputs (Standard Output) Asynchronous Master Reset Input (Active LOW) Serial Data Shift Right Input Clock Input (LOW to HIGH, Edge-triggered) Serial Data Shift Left Input Ground (0V) Positive Supply Voltage ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO IO ICC or IGND PD Tstg TL Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source Sink Current Per Output Pin (QA -QH) DC Output Source Sink Current Per Output Pin (QA’ -QH’) DC VCC or Ground Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 35 ± 235 ± 70 500 (*) -65 to +150 300 Unit V V V mA mA mA mA mA mW o o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnotimplied. (*) 500 mW: ≅ 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top tr, tf Supply Voltage Input Voltage Output Voltage Operating Temperature: M54HC Series M74HC Series Input Rise and Fall Time VCC = 2 V VCC = 4.5 V VCC = 6 V Parameter Value 2 to 6 0 to VCC 0 to VCC -55 to +125 -40 to +85 0 to 1000 0 to 500 0 to 400 Unit V V V o o C C ns 6/15 M54/M74HC299/323 DC SPECIFICATIONS Test Conditions Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 4.5 6.0 6.0 6.0 TA = 25 oC 54HC and 74HC Min. Typ. Max. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 2.0 4.4 4.5 5.9 6.0 4.18 4.31 5.68 5.8 4.18 4.31 5.68 5.8 0.0 0.1 0.0 0.1 0.0 0.1 0.17 0.26 0.18 0.26 0.17 0.26 0.18 0.26 ±0.1 ±0.5 4 Value -40 to 85 oC -55 to 125 oC 74HC 54HC Min. Max. Min. Max. 1.5 1.5 3.15 3.15 4.2 4.2 0.5 0.5 1.35 1.35 1.8 1.8 1.9 1.9 4.4 4.4 5.9 5.9 4.13 4.10 5.63 5.60 4.13 4.10 5.63 5.60 0.1 0.1 0.1 0.1 0.1 0.1 0.33 0.40 0.33 0.40 0.33 0.40 0.33 0.40 ±1 ±1 ±5 40 ±10 80 Unit VIH High Level Input V.


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