PDI1394P25BY

INTEGRATED CIRCUITS PDI1394P25BY 1-port 400 Mbps physical layer interface Product data 2002 Oct 11 Philips Semiconductors Philips Semiconductors Product data 1-port 400 Mbps physical layer interface PDI1394P25BY 1.0 FEATURES Fully supports provisions of IEEE 1394–1995 Standard for high performance serial bus and the P1394a–2000 Standard1 While unpowered and connected to the bus, will not drive TPBIAS on a connected port, even if receiving incoming bias voltage on that port Fully interoperable with Firewire™ and i.LINK™ implementations of the IEEE 1394 Standard.2 Supports extended bias-handshake time for enhanced interoperability with camcorders Full P1394a support includes: – Connection debounce – Arbitrated short reset – Multispeed concatenation – Arbitration acceleration – Fly-by concatenation – Port disable/suspend/resume Interface to link-layer controller supports both low-cost bus-holder isolation and optional Annex J electrical isolation Data interface to link-layer controller through 2/4/8 parallel lines at 49.152 MHz Low-cost 24.576 MHz crystal provides transmit, receive data at 100/200/400 Mbps, and link-layer controller clock at 49.152 MHz Provides one 1394a fully-compliant cable port at 100/200/400 Mbps. Can be used as a one port PHY without the use of any extra external components Does not require external filter capacitors for PLL Interoperable with link-layer controllers using 3.3 V and 5 V supplies Fully compliant with ...