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PDI1394P11BD Dataheets PDF



Part Number PDI1394P11BD
Manufacturers NXP
Logo NXP
Description 3-port physical layer interface
Datasheet PDI1394P11BD DatasheetPDI1394P11BD Datasheet (PDF)

INTEGRATED CIRCUITS PDI1394P11 3-port physical layer interface Product specification Supersedes data of 1998 Sep 24 1999 Apr 09 Philips Semiconductors Philips Semiconductors Product specification 3-port physical layer interface PDI1394P11 1.0 FEATURES • 3 cable interface ports • Supports 100Mb/s and 200Mb/s transfers • Interfaces to any 1394 standard Link Layer Controller • 5V tolerant I/Os with Bus Holders • Single 3.3V supply voltage • Arbitrated (short) Bus Reset (1394a feature) 3.0 O.

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INTEGRATED CIRCUITS PDI1394P11 3-port physical layer interface Product specification Supersedes data of 1998 Sep 24 1999 Apr 09 Philips Semiconductors Philips Semiconductors Product specification 3-port physical layer interface PDI1394P11 1.0 FEATURES • 3 cable interface ports • Supports 100Mb/s and 200Mb/s transfers • Interfaces to any 1394 standard Link Layer Controller • 5V tolerant I/Os with Bus Holders • Single 3.3V supply voltage • Arbitrated (short) Bus Reset (1394a feature) 3.0 ORDERING INFORMATION PACKAGE 64-pin plastic LQFP TEMPERATURE RANGE 0°C to +70°C 2.0 DESCRIPTION The Philips Semiconductors PDI1394P11 is an IEEE1394-1995 compliant Physical Layer interface. The PDI1394P11 provides the analog physical layer functions needed to implement a three port node in a cable-based IEEE 1394–1995 network. Additionally, the device manages bus initialization and arbitration cycles, as well as transmission and reception of data bits. The Link Layer Controller interface is compatible with both 3V and 5V Link Controllers. While providing a maximum transmission data rate of 200 Mb/s, the PDI1394P11 is compatible with current 100 Mb/s Physical Layer ICs. The PDI1394P11 is available in the LQFP64 package. OUTSIDE NORTH AMERICA PDI1394P11 BD NORTH AMERICA PDI1394P11 BD PKG. DWG. # SOT314-2 4.0 PIN CONFIGURATION PLLGND PLLVDD PLLGND FILTER DGND DGND AGND AGND 50 AVDD AGND 49 48 47 46 45 44 43 42 ISO– AVDD 51 XO 57 R1 R0 64 63 62 61 60 59 58 56 XI 55 54 53 RESET– LPS LREQ DVDD DVDD DVDD PD DGND SYSCLK DGND CTL0 CTL1 D0 D1 D2 D3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 52 TPBIAS3 TPBIAS2 TPBIAS1 TPA1+ TPA1– TPB1+ TPB1– AGND TPA2+ TPA2– TPB2+ TPB2– TPA3+ TPA3– TPB3+ TPB3– PDI1394P11 41 40 39 38 37 36 35 34 33 C/LKON PC2 PC1 AGND PC0 DGND DGND TESTM2 TESTM1 AGND CPS AVDD DVDD DVDD AVDD CNA SV00229 1999 Apr 09 2 853–2150 21222 Philips Semiconductors Product specification 3-port physical layer interface PDI1394P11 5.0 PIN DESCRIPTION PIN NUMBER 1 2 3 4 5, 6, 19, 20 7 8, 10, 17, 18, 63, 64 9 11, 12 13, 14, 15, 16 22, 21 PIN SYMBOL RESET– LPS LREQ DVDD DVDDD PD DGND SYSCLK CTL[0:1] D[0:3] TESTM[1:2] I/O I* I* I* I* I I* – O* I/O* I/O* I* NAME AND FUNCTION Power up reset, active LOW Link Layer Controller (LLC) power status Link request from controller Should be connected to the LLC VDD supply when a 5V LLC is connected to the Phy, and should be connected to the Phy DVDD when a 3V LLC is used. Digital circuit power Device power down input Digital circuit ground 49.152 MHz clock to link controller Link interface bi-directional control signals Link interface bi-directional data signals Test/Mode Control pins 11 =1394–1995 mode 10 = 1394a mode 00/01 = Reserved Cable power status Analog circuit power Analog circuit ground Bus/Isochronous Resource Manager capable input, or LINK-ON signal output Power class bits 0 through 2 inputs Cable Not Active output Port n cable pair A, positive signal Port n cable pair A, negative signal Port n cable pair B, positive signal Port n cable pair B, negative signal Cable termination voltage supplies PLL circuit ground PLL external filter capacitor Crystal oscillator connection Crystal oscillator connection PLL circuit power External current setting resistor Link interface isolation status input 23 24, 25, 51, 55 26, 32, 41, 49, 50, 61 27 30, 29, 28 31 36, 40, 45 35, 39, 44 34, 38, 43 33, 37, 42 46, 47, 48 52, 53 54 56 57 58 59, 60 62 CPS AVDD AGND C/LKON PC[0:2] CNA TPA[1:3]+ TPA[1:3]– TPB[1:3]+ TPB[1:3]– TPBIAS[1:3] PLLGND FILTER XI XO PLLVDD R[0:1] ISO– I – – I/O* I* O* I/O I/O I/O I/O O – I/O I O – – I* NOTE: * Indicates 5V tolerant structure. 1999 Apr 09 3 Philips Semiconductors Product specification 3-port physical layer interface PDI1394P11 6.0 BLOCK DIAGRAM CPS LPS ISO– CNA RECEIVED DATA DECODER/ TIMER R0 BIAS VOLTAGE AND CURRENT GENERATOR R1 TPBIAS1 TPBIAS2 TPBIAS3 SYSCLK LREQ CTL0 CTL1 D0 D1 D2 D3 ARBITRATION AND CONTROL STATE MACHINE LOGIC LINK INTERFACE PORT 1 TPA1+ TPA1– TPB1+ TPB1– PC0 PC1 PC2 C/LKON TPA2+ TPA2– PORT 2 TPB2+ TPB2– TPA3+ TPA3– TPB3+ TPB3– TESTM1 TESTM2 PORT 3 RESET– PD TRANSMIT DATA ENCODER CRYSTAL OSCILLATOR PLL SYSTEM & TRANSMIT CLOCK GENERATOR XI XO FILTER SV00228 7.0 FUNCTIONAL SPECIFICATION The PDI1394P11 is an IEEE1394–1995 High Performance Serial Bus Specification compliant physical layer interface device. It provides an interface between an attached link layer controller and three 1394 cable interface ports. In addition to the interface function, the PDI1394P11 performs bus initialization and arbitration functions as well as monitoring line conditions and connection status. monitor conditions on the cable to determine connection status, data speed, and bus arbitration states. The PDI1394P11 receives data to be transmitted over the bus from two or four parallel data paths to the Link Controller, D[0:3]. These data paths are latched a.


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