EDE5104GBSA

PRELIMINARY DATA SHEET 512M bits DDR-II SDRAM EDE5104GBSA (128M words × 4 bits) EDE5108GBSA (64M words × 8 bits) EDE5116GBSA (32M words × 16 bits) Description The EDE5104GB is a 512M bits DDR-II SDRAM organized as 33,554,432 words × 4 bits × 4 banks. The EDE5108GB is a 512M bits DDR-II SDRAM organized as 16,777,216 words × 8 bits × 4 banks. It packaged in 64-ball µBGA package. The EDE5116GB is a 512M bits DDR-II SDRAM organized as 8,388,608 words × 16 bits × 4 banks. It is packaged in 84-ball µBGA package. Features 1.8V power supply Double-data-rate architecture: two data transfers per clock cycle Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver DQS is edge aligned with data for READs: centeraligned with data for WRITEs Differential clock inputs (CK and /CK) DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS Four internal banks for concurrent operation Data mask (DM) for write data Burst lengths: 4, 8 /CAS Latency (CL): 3, 4, 5 Auto precharge operation for each burst access Auto refresh and self refresh modes 7.8µs average periodic refresh interval 1.8V (SSTL_18 compatible) I/O Posted CAS by programmable additive latency for better command and data bus efficiency Off-Chip-Driver Impedance Adjustment and On-DieTermination for better signal quality Programmab...