Document
IA6805E2 Microprocessor Unit
FEATURES
Preliminary Data Sheet
• Form, Fit, and Function Compatible with the Harris© CDP6805E2CE and Motorola© MC146805E2 • Internal 8-bit Timer with 7-Bit Programmable Prescaler • On-chip Clock • Memory Mapped I/O • Versatile Interrupt Handling • True Bit Manipulation • Bit Test and Branch Instruction • Vectored Interrupts • Power-saving STOP and WAIT Modes • Fully Static Operation • 112 Bytes of RAM
The IA6805E2 is a "plug-and-play" drop-in replacement for the original IC. innovASIC produces replacement ICs using its MILESTM, or Managed IC Lifetime Extension System, cloning technology. This technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon technology advances. MILESTM also verifies the clone against the original IC so that even the "undocumented features" are duplicated. This data sheet documents all necessary engineering information about the IA6805E2 including functional and I/O descriptions, electrical characteristics, and applicable timing.
Functional Block Diagram
RESET_N
OSC1
VDD
IRQ_N LI DS RW_N AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 A12 A11 A10 A9 A8 VSS
(3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20)
40 Pin DIP
(38) (37) (36) (35) (34) (33) (32) (31) (30) (29) (28) (27) (26) (25) (24) (23) (22) (21)
OSC2 (6) (5) (4) (3) (2) (1) (44) (43) (42) (41) (40) TIMER PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 B0 B1 B2 B3 B4 B5 A12 A11 A10 VSS A9 A8 B7 B6 B5 B4 B6 B7 NC AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 NC NC (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28)
LI
(2)
(39)
OSC1
PB0
NC
DS
IA6805E2
OSC2
RESET_N
(1)
(40)
VDD
TIMER
IRQ_N
RW_N
(39) (38)
PB1 PB2 PB3 PB4 PB5 PB6 PB7 B0 B1 B2 B3
IA6805E2 44 Pin LCC
(37) (36) (35) (34) (33) (32) (31) (30) (29)
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IA6805E2 Microprocessor Unit
Preliminary Data Sheet
Figure 1 illustrates the IA6805E2. The IA6805E2 (CMOS) Microprocessor Unit (MPU) is a low cost, low power MPU. It features a CPU, on-chip RAM, parallel I/O compatibility with pins programmable as input or output. The following paragraphs will further describe this system block diagram and design in more detail. Figure 1: System Block Diagram
TIMER
PRESCALER
TIMER/ COUNTER
OSC1
OSC2 RESET_N
TIMER CONTROL
OSCILLATOR
LI IRQ_N
PA0 B0 ACCUMULATOR 8 PORT A REG DATA DIR REG INDEX REGISTER 8 X CONDITION CODE 5 REGISTER CC STACK POINTER 6 SP PROGRAM COUNTER HIGH PCH 5 PROGRAM COUNTER LOW PCL 8 ALU ADDRESS DRIVE A CPU CONTROL MUX BUS DRIVE B1 B2 B3 B4 B5 B6 B7 MULTIPLEXED ADDRESS DATA BUS
PA0 PA1 PA2 PORT A I/O LINES PA3 PA4 PA5 PA6 PA7
CPU
PB0 PB1 PB2 PORT B I/O LINES PB3 PB4 PB5 PB6 PB7 PORT B REG DATA DIR REG
A8 A9 A10 A11 A12 ADDRES.