Document
2M x 8-Bit Dynamic RAM
HYB5117800BSJ-50/-60/-70
Advanced Information
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2 097 152 words by 8-bit organization 0 to 70 °C operating temperature Performance:: -50 tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time 50 13 25 90 35 -60 60 15 30 110 40 -70 70 20 35 130 45 ns ns ns ns ns
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Single + 5 V (± 10 %) supply Low power dissipation max. 660 active mW (-50 version) max. 605 active mW (-60 version) max. 550 active mW (-70 version) 11 mW standby (TTL) 5.5. mW standby (CMOS) Output unlatched at cycle end allows two-dimensional chip selection Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh, self refresh and test mode Fast page mode capability All inputs, outputs and clocks fully TTL-compatible 2048 refresh cycles / 32 ms Plastic Package: P-SOJ-28-3 400 mil
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Semiconductor Group
1
1.96
HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM
The HYB 5117800BSJ is a 16 MBit dynamic RAM organized as 2097152 words by 8-bits. The HYB 5117800BSJ utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5117800BSJ to be packaged in a standard SOJ 28 400 mil plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. System-oriented features include single + 5 V (± 10 %) power supply, direct interfacing with high-performance logic device families such as Schottky TTL. Ordering Information Type HYB 5117800BSJ-50 HYB 5117800BSJ-60 HYB 5117800BSJ-70 Pin Names A0 to A10 A0 to A9 RAS OE I/O1-I/O8 CAS WE Row Address Inputs Column Address Inputs Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply (+ 5 V) Ground (0 V) not connected Ordering Code Q67100-Q1092 Q67100-Q1093 Q67100-Q1094 Package P-SOJ-28-3 P-SOJ-28-3 P-SOJ-28-3 400 mil 400 mil 400 mil Descriptions DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns)
VCC VSS
N.C.
Semiconductor Group
2
HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM
P-SOJ-28-3 (400mil)
VCC I/O1 I/O2 I/O3 I/O4 WE RAS N.C. A10 A0 A1 A2 A3 VCC
O 1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VSS I/O8 I/O7 I/O6 I/O5 CAS OE A9 A8 A7 A6 A5 A4 VSS
Pin Configuration
Semiconductor Group
3
HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM
I/O1 I/O2
I/O8
WE CAS
.
&
Data in Buffer
No. 2 Clock Generator 8
Data out Buffer
8
OE
10
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
11
Column Address Buffer(10)
10
Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
8
Refresh Counter (11) 11 Row
1024 x8
Address Buffers(11)
11
Decoder 2048
Row
Memory Array 2048x1024x8
RAS
No. 1 Clock
Generator
Voltage Down Generator
VCC VCC (internal)
Block Diagram
Semiconductor Group
4
HYB 5117800.