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HYB5117400BT-60 Dataheets PDF



Part Number HYB5117400BT-60
Manufacturers Siemens
Logo Siemens
Description 4M x 4-Bit Dynamic RAM
Datasheet HYB5117400BT-60 DatasheetHYB5117400BT-60 Datasheet (PDF)

4M x 4-Bit Dynamic RAM HYB5117400BJ -50/-60/-70 HYB5117400BT -50/-60/-70 Advanced Information • • • 4 194 304 words by 4-bit organization 0 to 70 °C operating temperature Performance: -50 tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time 50 13 25 90 35 -60 60 15 30 110 40 -70 70 20 35 130 45 ns ns ns ns ns • • Single + 5 V (± 10 %) supply Low power dissipation max. 660 active mW (-50 version) max. 605 active mW (-6.

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4M x 4-Bit Dynamic RAM HYB5117400BJ -50/-60/-70 HYB5117400BT -50/-60/-70 Advanced Information • • • 4 194 304 words by 4-bit organization 0 to 70 °C operating temperature Performance: -50 tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time 50 13 25 90 35 -60 60 15 30 110 40 -70 70 20 35 130 45 ns ns ns ns ns • • Single + 5 V (± 10 %) supply Low power dissipation max. 660 active mW (-50 version) max. 605 active mW (-60 version) max. 550 active mW (-70 version) 11 mW standby (TTL) 5.5. mW standby (MOS) Output unlatched at cycle end allows two-dimensional chip selection Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh, self refresh and test mode Fast page mode capability All inputs, outputs and clocks fully TTL-compatible 2048 refresh cycles / 32 ms Plastic Package: P-SOJ-26/24 300 mil P TSOPII-26/24 300 mil • • • • • • Semiconductor Group 1 1.96 HYB 5117400BJ/BT-50/-60/-70 4M x 4-DRAM The HYB 5117400BJ/BT is a 16MBit dynamic RAM organized as 4194304 words by 4-bits. The HYB 5117400BJ/BT utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5117400BJ/BT to be packaged in a standard SOJ 26/24 or TSOPII-26/24 plastic package, both with 300 mil width. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. System-oriented features include single + 5 V (± 10 %) power supply, direct interfacing with high-performance logic device families such as Schottky TTL. Ordering Information Type HYB 5117400BJ-50 HYB 5117400BJ-60 HYB 5117400BJ-70 HYB 5117400BT-50 HYB 5117400BT-60 HYB 5117400BT-70 Pin Names A0 to A10 A0 to A10 RAS OE I/O1-I/O4 CAS WE Row Address Inputs Column Address Inputs Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply (+ 5 V) Ground (0 V) not connected Ordering Code Q67100-Q1086 Q67100-Q1087 Q67100-Q1088 on request on request on request Package P-SOJ-26/24 300 mil P-SOJ-26/24 300 mil P-SOJ-26/24 300 mil P-TSOPII-26/24 300mil P-TSOPII-26/24 300mil P-TSOPII-26/24 300mil Descriptions DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) VCC VSS N.C. Semiconductor Group 2 HYB 5117400BJ/BT-50/-60/-70 4M x 4-DRAM Vcc I/O1 I/O2 WE RAS N.C. A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 Vss I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 Vss P-SOJ-26/24 300 mil P-TSOPII-26/24 300 mil Pin Configuration Semiconductor Group 3 HYB 5117400BJ/BT-50/-60/-70 4M x 4-DRAM I/O1 I/O2 I/O3 I/O4 WE CAS . & Data in Buffer No. 2 Clock Generator Data out Buffer 4 OE 4 11 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 11 Column Address.


HYB5117400BT-50 HYB5117400BT-60 HYB5117400BT-70


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