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74LVC109 Dataheets PDF



Part Number 74LVC109
Manufacturers Philips
Logo Philips
Description Dual JK flip-flop
Datasheet 74LVC109 Datasheet74LVC109 Datasheet (PDF)

INTEGRATED CIRCUITS 74LVC109 Dual JK flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of 1997 Mar 18 IC24 Data Handbook 1998 Apr 28 Philips Semiconductors Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74LVC109 FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct interfac.

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INTEGRATED CIRCUITS 74LVC109 Dual JK flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of 1997 Mar 18 IC24 Data Handbook 1998 Apr 28 Philips Semiconductors Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74LVC109 FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct interface with TTL levels • Output capability: standard • ICC category: flip-flops DESCRIPTION The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. The 74LVC109 is a dual positive-edge triggered JK-type flip-flop featuring individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by tying the J and K inputs together. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL tPHL/tPLH fmax CI CPD PARAMETER Propagation delay nCP to nQ, nQ nSD to nQ, nQ nRD to nQ, nQ Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop VI = GND to VCC1 CONDITIONS TYPICAL 4.0 4.5 4.5 250 5.0 27 UNIT ns MHz pF pF CL = 50 pF; VCC = 3.3 V NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi )Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION PACKAGES 16-Pin Plastic SO 16-Pin Plastic SSOP Type II 16-Pin Plastic TSSOP Type I TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C –40°C to +85°C OUTSIDE NORTH AMERICA 74LVC109 D 74LVC109 DB 74LVC109 PW NORTH AMERICA 74LVC109 D 74LVC109 DB 74LVC109PW DH PKG. DWG. # SOT109-1 SOT338-1 SOT403-1 PIN CONFIGURATION 1R D 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V CC 2R 2J 2K 2CP 2S D D PIN DESCRIPTION PIN NUMBER 1, 15 2, 14, 3, 13 4, 12 5, 11 6, 10 7, 9 8 16 SYMBOL 1RD, 2RD 1J, 2J, 1K, 2K 1CP, 2CP 1SD, 2SD 1Q, 2Q 1Q, 2Q GND VCC FUNCTION Asynchronous reset input (active LOW) Synchronous inputs; flip-flops 1 and 2 Clock input (LOW-to-HIGH, edge-triggered) Asynchronous set inputs (active LOW) True flip-flop outputs Complement flip-flop outputs Ground (O V) Positive supply voltage 1J 1K 1CP 1S D 1Q 1Q GND 2Q 2Q SV00517 1998 Apr 28 2 853–1947 19308 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74LVC109 LOGIC SYMBOL (IEEE/IEC) 5 S 2 1J 4 C1 3 1K 1 R 15 R 7 13 1K 12 C1 9 6 14 1J 11 S 10 FUNCTIONAL DIAGRAM 5 1SD 1J SD J Q FF1 Q RD 1 1RD 11 2SD SD (b) 14 2J J Q FF2 Q RD 2Q 9 2Q 10 1Q 7 1Q 6 2 4 1CP CP 3 1K K (a) SV00519 12 2CP CP LOGIC SYMBOL 5 11 1S D 2S D 13 2K K 15 2RD SV00520 2 1J 14 2J 4 1CP 12 2CP 3 1K 13 2K J Q 1Q 6 2Q 10 CP 1Q 7 K Q 2Q 9 1R D 2R D 1 15 SV00518 LOGIC DIAGRAM K C C C C Q Q J C S C C C R C C CP SV00521 1998 Apr 28 3 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74LVC109 FUNCTION TABLE INPUTS OPERATING MODES Asynchronous set Asynchronous reset Undetermined Toggle Load “0” (reset) Load “1” (set) Hold “no change” nSD L H L H H H H nRD H L L H H H H nCP X X X ↑ ↑ ↑ ↑ nJ X X X h l h l nK X X X l l h h nQ H L H q L H q OUTPUTS nQ L H H q H L q NOTES: H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition. X = don’t care ↑ = LOW-to-HIGH CP transition RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr, tf PARAMETER DC supply voltage (for max. speed performance) DC supply voltage (for low-voltage applications) DC input voltage range DC output voltage range Operating free-air temperature range Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS LIMITS MIN 2.7 1.2 0 0 –40 0 0 MAX 3.6 3.6 5.5 VCC +85 20 10 UNIT V V V °C ns/V ABSOLUTE MAXIMUM RATINGS1 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink c.


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