74LV273

INTEGRATED CIRCUITS 74LV273 Octal D-type flip-flop with reset; positive-edge trigger Product specification Supersedes data of 1997 Apr 07 IC24 Data Handbook 1998 May 29 Philips Semiconductors Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger 74LV273 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for Low Voltage applications: 1.0 to 3.6V Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V Typical VOLP (output ground bounce) t 0.8V @ VCC = 3.3V, Typical VOHV (output VOH undershoot) u 2V @ VCC = 3.3V, Ideal buffer for MOS microprocessor or memory Common clock and master reset Output capability: standard ICC category: MSI QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr =tf v2.5 ns SYMBOL tPHL/tPLH fmax CI CPD PARAMETER Propagation delay CP to Qn; MR to Qn Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop Tamb = 25°C Tamb = 25°C DESCRIPTION The 74LV273 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT273. The 74LV273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW independently of clock or data inp...