74LV20

INTEGRATED CIRCUITS 74LV20 Dual 4-input NAND gate Product specification Supersedes data of 1997 Mar 28 IC24 Data Handbook 1998 Apr 20 Philips Semiconductors Philips Semiconductors Product specification Dual 4-input NAND gate 74LV20 FEATURES Optimized for Low Voltage applications: 1.0 to 3.6V Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V Typical VOLP (output ground bounce) t 0.8V @ VCC = 3.3V, Typical VOHV (output VOH undershoot) u 2V @ VCC = 3.3V, Output capability: standard ICC category: SSI QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr =tf v2.5 ns SYMBOL tPHL/tPLH CI CPD PARAMETER Propagation delay nA, nB, nC, nD to nY Input capacitance Power dissipation capacitance per gate Tamb = 25°C Tamb = 25°C DESCRIPTION The 74LV20 is a low–voltage Si–gate CMOS device and is pin and function compatible with 74HC/HCT20. The 74LV20 provides the 4–input NAND function. CONDITIONS CL = 15pF VCC = 3.3V Notes 1 and 2 TYPICAL 8 3.5 22 UNIT ns pF pF NOTES: 1 CPD is used to determine the dynamic power dissipation (PD in µW) VCC2 x fi )S (CL VCC2 fo) where: PD = CPD fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; VCC2 fo) = sum of the outputs. S (CL 2 The condition is VI = GND to VCC ORDERING INFORMATION PACKAGES 14-Pin Plastic DIL 14-Pin Plastic SO 14-Pin Plastic SSOP Type II 14-Pin Plastic TSSOP Type I TEMPERATURE RANGE –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°...