74LV10

INTEGRATED CIRCUITS 74LV10 Triple 3-input NAND gate Product specification Supersedes data of 1997 Feb 12 IC24 Data Handbook 1998 Apr 20 Philips Semiconductors Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 FEATURES Optimized for Low Voltage applications: 1.0 to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Output capability: standard ICC category: SSI QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf v2.5 ns SYMBOL tPHL/tPLH CI CPD PARAMETER Propagation delay nA, nB, nC to nY Input capacitance Power dissipation capacitance per gate Tamb = 25°C. Tamb = 25°C. DESCRIPTION The 74LV10 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT10. The 74LV10 provides the 3-input NAND function. CONDITIONS CL = 15 pF; VCC = 3.3 V See Notes 1 and 2 TYPICAL 9 3.5 12 UNIT ns pF pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) VCC2 fo) where: PD = CPD × VCC2 × fi )ȍ (CL fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; ȍ (CL VCC2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC ORDERING INFORMATION PACKAGES 14-Pin Plastic DIL 14-Pin Plastic SO 14-Pin Plastic SSOP Type II 14-Pin Plastic TSSOP Type I TEMPERATURE RANGE –40°C to +125°C –40°C to +125°C –40°C ...