SN54/74LS490 DUAL DECADE COUNTER
The SN54 / 74LS490 contains a pair of high-speed 4-stage ripple counters. Each half of ...
SN54/74LS490 DUAL DECADE COUNTER
The SN54 / 74LS490 contains a pair of high-speed 4-stage ripple counters. Each half of the SN54 / 74LS490 has individual Clock, Master Reset and Master Set (Preset 9) inputs. Each section counts in the 8, 4, 2, 1 BCD code.
Dual Version of SN54 / 74LS490 Individual Asynchronous Clear and Preset to 9 for Each Counter Count Frequency — Typically 65 MHz Input Clamp Diodes Limit High-Speed Termination Effects
DUAL DECADE COUNTER
LOW POWER
SCHOTTKY
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 16 CPb 15 MRb 14 Q0b 13 MSb 12 Q1b 11 Q2b 10 Q3b 9
16 1
J SUFFIX CERAMIC CASE 620-09
1 CPa
2 MRa
3 Q0a
4 MSa
5 Q1a
6 Q2a
7 Q3a
8 GND
16 1
N SUFFIX PLASTIC CASE 648-08
PIN NAMES
LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 1.5 U.L. 5 (2.5) U.L.
16 1
MS MR CP Q0 – Q3
Master Set (Set to 9) Input Master Reset Clock Input (Active LOW Going Edge) Counter Outputs (Note b)
0.5 U.L. 0.5 U.L. 1.5 U.L. 10 U.L.
D SUFFIX SOIC CASE 751B-03
NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.
ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC
LOGIC DIAGRAM (ONE HALF SHOWN)
MS 4 12
TRUTH TABLE
OUTPUTS COUNT 0 1 2 Q3 L L L L L L L L H H Q2 L L L L H H H H L L Q1 L L H H L L H H L L Q0 L H L H L H L H L H
CP
1 15 K CD 2 14 3 Q0 13 5 Q1 11 6 Q2 10 7 Q3 9 J SD Q K CD J Q K CD J Q K CP J CD SD Q
3 4 5 6 7 8 9
MR
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