74HCT4510

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4510 BCD up/down counter Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors BCD up/down counter Product specification 74HC/HCT4510 FEATURES Output capability: standard ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4510 are high-speed Si-gate CMOS devices and are pin compatible with the “4510” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4510 are edge-triggered synchronous up/down BCD counters with a clock input (CP), an up/down count control input (UP/DN), an active LOW count enable input (CE), an asynchronous active HIGH parallel load input (PL), four parallel inputs (D0 to D3), four parallel outputs (Q0 to Q3), an active LOW terminal count output (TC), and an overriding asynchronous master reset input (MR). Information on D0 to D3 is loaded into the counter while PL is HIGH, independent of all other input conditions except the MR input, which must be LOW. With PL LOW, the counter changes on the LOW-to-HIGH transition of CP if CE is LOW. UP/DN determines the direction of the count, HIGH for counting up, LOW for counting down. When counting up, TC is LOW when Q0 and Q3 are HIGH and CE is LOW. When counting down, TC is L...