74HCT4024

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4024 7-stage binary ripple counter Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors 7-stage binary ripple counter Product specification 74HC/HCT4024 FEATURES Output capability: standard ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4024 are high-speed Si-gate CMOS devices and are pin compatible with the “4024” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4024 are 7-stage binary ripple counters with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. APPLICATIONS Frequency dividing circuits Time delay circuits QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns SYMBOL PARAMETER CONDITIONS tPHL/ tPLH fmax CI CPD propagation delay CP to Q0 maximum clock frequency input capacitance power dissipation capacitance per pa...