Document
IDT54/74FCT240/244T/AT/CT/DT - 2240/2244T/AT/CT, IDT54/74FCT540/541/2541T/AT/CT FAST CMOS OCTAL BUFFER/LINE DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES IDT54/74FCT240T/AT/CT/DT - 2240T/AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVERS
IDT54/74FCT244T/AT/CT/DT - 2244T/AT/CT IDT54/74FCT540T/AT/CT IDT54/74FCT541/2541T/AT/CT
Integrated Device Technology, Inc.
FEATURES:
• Common features: – Low input and output leakage ≤1µA (max.) – CMOS power levels – True TTL input and output compatibility – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) – Meets or exceeds JEDEC standard 18 specifications – Product available in Radiation Tolerant and Radiation Enhanced versions – Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) – Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages • Features for FCT240T/FCT244T/FCT540T/FCT541T: – Std., A, C and D speed grades – High drive outputs (-15mA IOH, 64mA IOL) • Features for FCT2240T/FCT2244T/FCT2541T: – Std., A and C speed grades – Resistor outputs (-15mA IOH, 12mA IOL Com.) (-12mA IOH, 12mA IOL Mil.) – Reduced system switching noise
DESCRIPTION:
The IDT octal buffer/line drivers are built using an advanced dual metal CMOS technology. The FCT240T/FCT2240T and FCT244T/FCT2244T are designed to be employed as memory and address drivers, clock drivers and bus-oriented transmitter/receivers which provide improved board density. The FCT540T and FCT541T/FCT2541T are similar in function to the FCT240T/FCT2240T and FCT244T/FCT2244T, respectively, except that the inputs and outputs are on opposite sides of the package. This pinout arrangement makes these devices especially useful as output ports for microprocessors and as backplane drivers, allowing ease of layout and greater board density. The FCT2240T, FCT2244T and FCT2541T have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall times-reducing the need for external series terminating resistors. FCT2xxxT parts are plug-in replacements for FCTxxxT parts.
FUNCTIONAL BLOCK DIAGRAMS
OE A OE B
DA0
OE A
DA0 OB0 DA1 OB1 DA2 OB2 DA3 OB3
OE A OE B
OA0 DB0 OA1 DB1 OA2 DB2 OA3 DB3 D0 D1 D2 D3 D4 D5 D6 D7
OE B
O0 O1 O2 O3 O4 O5 O6 O7
OA0
DB0
OB0
DA1
OA1
DB1
OB1
DA2
OA2
DB2
OB2
DA3 OB3
OA3
DB3
FCT240/2240T
FCT244/2244T
FCT540/541/2541T *Logic diagram shown for 'FCT540. 'FCT541/2541T is the non-inverting option.
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
DECEMBER 1995
DSC-2565/6
6.8 6.8
1
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IDT54/74FCT240/244T/AT/CT/DT - 2240/2244T/AT/CT, IDT54/74FCT540/541/2541T/AT/CT FAST CMOS OCTAL BUFFER/LINE DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
FCT240/2240T
OEA DA0 OB0 DA1 OB1 DA2 OB2 DA3 OB3 GND 1 2 3 4 5 6 7 8 9 10 P20-1 D20-1 SO20-2 SO20-7 SO20-8 & E20-1 20 19 18 17 16 15 14 13 12 11 VCC OEB OA0 DB0 OA1 DB1 OA2 DB2 OA3 DB3 DA1 OB1 DA2 OB2 DA3 4 5 6 7 8 L20-2
3 2
1
OEA V CC
20 19 18 17 16 15
OEB
DA 0
INDEX
OB 0
OA0 DB0 OA1 DB1 OA2
14 9 10 11 12 13
GND
OB3
DB 3
OA3
DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW
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LCC TOP VIEW
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FCT244/2244T
OEA DA 0 OB0 DA 1 OB1 DA 2 OB2 DA 3 OB3 GND 1 2 3 4 5 6 7 8 9 10 20 19 P20-1 D20-1 SO20-2 SO20-7 SO20-8 & E20-1 18 17 16 15 14 13 12 11 VCC OEB OA0 DB 0 OA1 DB 1 OA2 DB 2 OA3 DB 3 3 2 DA 1 OB1 DA 2 OB2 DA 3 4 5 6 7 8 L20-2 1 20 19 18 17 16 15 14 9 10 11 12 13
OB3 GND DB 3 OA3 DB 2 DA 0
INDEX
OEB*
OEA VCC
OB0
DB 2
OA0 DB 0 OA1 DB 1 OA2
DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW
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LCC TOP VIEW
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FCT540/541/2541T
OEA V CC D1 D0
OEA D0 D1 D2 D3 D4 D5 D6 D7 GND
1 2 3 4 5 6 7 8 9 10 P20-1 D20-1 SO20-2 SO20-8 & E20-1
20 19 18 17 16 15 14 13 12 11
VCC OEB O 0* O 1* O 2* O 3* O 4* O 5* O 6* O 7*
3 2 D2 D3 D4 D5 D6 4 5 6 7 8
1
20 19 18 17 16 15
OEB
INDEX
O 0* O 1* O 2* O 3* O 4*
L20-2
14 9 10 11 12 13
D7 GND O 6* O 7* O 5*
DIP/SOIC/QSOP/CERPACK TOP VIEW
*Ox for 540, Ox for 541/2541T
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LCC TOP VIEW
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6.8
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IDT54/74FCT240/244T/AT/CT/DT - 2240/2244T/AT/CT, IDT54/74FCT540/541/2541T/AT/CT FAST CMOS OCTAL BUFFER/LINE DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names OEA, OEB Dxx Oxx Description 3–State Output Enable Inputs (Active LOW) Inputs Outputs
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FUNCTION TABLE
Inputs(1)
OEA
L L H
OEB
L L H
D L H X
240 H L Z
Outputs(1) 244 540
L H
541
L
H Z
L Z
H Z
2565 tbl 02
NOTES: 1. H = High Voltage Level X = Don’t Care L = Low Voltage Level Z = High Impedance
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Commercial VTERM(2) Terminal Voltage –0.5 to +7.0 with Respect to GND VTERM(3) Terminal Voltage –0.5 to with Respect to VCC +0.5 GND TA Operating 0 to +70 Temperature TBIAS Temperature –55 to +125 Under Bias TSTG Storage –55 to +125 Temperature PT Power Dissipation 0.5 I OUT DC Output Current –60 to +12.