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IDT72V3670 Dataheets PDF



Part Number IDT72V3670
Manufacturers Integrated Device Tech
Logo Integrated Device Tech
Description CMOS FIFO memories
Datasheet IDT72V3670 DatasheetIDT72V3670 Datasheet (PDF)

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO 1,024 x 36, 2,048 x 36 4,096 x 36, 8,192 x 36 16,384 x 36, 32,768 x 36 65,536 x36, 131,072 x 36 IDT72V3640, IDT72V3650 IDT72V3660, IDT72V3670 IDT72V3680, IDT72V3690 IDT72V36100, IDT72V36110 • • • • • • • • • • • • • • • FEATURES: • • • • • • Choose among the following memory organizations:Commercial IDT72V3640  1,024 x 36 IDT72V3650  2,048 x 36 IDT72V3660  4,096 x 36 IDT72V3670  8,192 x 36 IDT72V3680  16,384 x 36 IDT72V3690  32,768 x 36.

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3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO 1,024 x 36, 2,048 x 36 4,096 x 36, 8,192 x 36 16,384 x 36, 32,768 x 36 65,536 x36, 131,072 x 36 IDT72V3640, IDT72V3650 IDT72V3660, IDT72V3670 IDT72V3680, IDT72V3690 IDT72V36100, IDT72V36110 • • • • • • • • • • • • • • • FEATURES: • • • • • • Choose among the following memory organizations:Commercial IDT72V3640  1,024 x 36 IDT72V3650  2,048 x 36 IDT72V3660  4,096 x 36 IDT72V3670  8,192 x 36 IDT72V3680  16,384 x 36 IDT72V3690  32,768 x 36 IDT72V36100  65,536 x 36 IDT72V36110  131,072 x 36 133 MHz operation (7.5 ns read/write cycle time) User selectable input and output port bus-sizing - x36 in to x36 out - x36 in to x18 out - x36 in to x9 out - x18 in to x36 out - x9 in to x36 out Big-Endian/Little-Endian user selectable byte representation 5V input tolerant Fixed, low first word latency Zero latency retransmit Auto power down minimizes standby power consumption Master Reset clears entire FIFO Partial Reset clears data, but retains programmable settings Empty, Full and Half-Full flags signal FIFO status Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags Program programmable flags by either serial or parallel means Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) Output enable puts data outputs into high impedance state Easily expandable in depth and width Independent Read and Write Clocks (permit reading and writing simultaneously) Available in the 128-pin Thin Quad Flat Pack (TQFP) High-performance submicron CMOS technology Industrial temperature range (–40°C to +85°C) is available FUNCTIONAL BLOCK DIAGRAM D0 -Dn (x36, x18 or x9) WEN WCLK LD SEN INPUT REGISTER OFFSET REGISTER FF/IR PAF EF/OR PAE HF FWFT/SI PFM FSEL0 FSEL1 WRITE CONTROL LOGIC FLAG LOGIC RAM ARRAY 1,024 x 36, 2,048 x 36 4,096 x 36, 8,192 x 36 16,384 x 36, 32,768 x 36 65,536 x 36, 131,072 x36 WRITE POINTER READ POINTER BE IP BM IW OW MRS PRS CONTROL LOGIC BUS CONFIGURATION RESET LOGIC OUTPUT REGISTER READ CONTROL LOGIC RT RM RCLK REN OE Q0 -Qn (x36, x18 or x9) 4667 drw 01 The SuperSync II FIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 © 2001 Integrated Device Technology, Inc. APRIL 2001 DSC-4667/3 IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES DESCRIPTION: The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690/ 72V36100/72V36110 are exceptionally deep, high speed, CMOS First-InFirst-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. These FIFOs offer several key user benefits: • Flexible x36/x18/x9 Bus-Matching on both read and write ports • The period required by the retransmit operation is fixed and short. • The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short. • High density offerings up to 4 Mbit Bus-Matching Sync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the state of external control pins Input Width (IW), Output Width (OW), and BusMatching (BM) pin during the Master Reset cycle. The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data is read from the FIFO on every rising edge PIN CONFIGURATIONS INDEX 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 WCLK PRS MRS LD FWFT/SI FF/IR VCC PAF GND OW FS0 HF GND FS1 BE IP BM VCC PAE PFM EF/OR RM GND RCLK REN RT WEN SEN DNC(1) VCC DNC(1) IW D35 D34 D33 D32 VCC D31 D30 GND D29 D28 D27 D26 D25 D24 D23 GND D22 VCC D21 D20 D19 D18 GND D17 D16 D15 D14 D13 VCC D12 GND D11 D10 D9 D8 D7 D6 GND D5 D4 D3 VCC D2 D1 D0 GND Q0 Q1 Q2 Q3 Q4 Q5 GND Q6 VCC Q7 Q8 Q9 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 39 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 OE VCC VCC Q35 Q34 Q33 Q32 GND GND Q31 Q30 Q29 Q28 Q27 Q26 VCC Q25 Q24 GND GND Q23 Q22 Q21 Q20 Q19 Q18 .


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