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55N03LTA Dataheets PDF



Part Number 55N03LTA
Manufacturers Philips
Logo Philips
Description Logic Level FET
Datasheet 55N03LTA Datasheet55N03LTA Datasheet (PDF)

PHP/PHB/PHD55N03LTA TrenchMOS™ Logic Level FET Rev. 04 — 4 September 2002 Product data 1. Description N-channel logic level field-effect power transistor in a plastic package using TrenchMOS™ technology. Product availability: PHP55N03LTA in a SOT78 (TO-220AB) PHB55N03LTA in a SOT404 (D2-PAK) PHD55N03LTA in a SOT428 (D-PAK). 2. Features s Low on-state resistance s Fast switching. 3. Applications s Computer motherboard high frequency DC to DC converters. 4. Pinning information Table 1: Pinning .

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PHP/PHB/PHD55N03LTA TrenchMOS™ Logic Level FET Rev. 04 — 4 September 2002 Product data 1. Description N-channel logic level field-effect power transistor in a plastic package using TrenchMOS™ technology. Product availability: PHP55N03LTA in a SOT78 (TO-220AB) PHB55N03LTA in a SOT404 (D2-PAK) PHD55N03LTA in a SOT428 (D-PAK). 2. Features s Low on-state resistance s Fast switching. 3. Applications s Computer motherboard high frequency DC to DC converters. 4. Pinning information Table 1: Pinning - SOT78, SOT404, SOT428 simplified outlines and symbol Simplified outline mb mb mb Pin Description 1 2 3 mb gate (g) drain (d) source (s) mounting base, connected to drain (d) [1] Symbol d g s 2 2 1 MBK106 MBB076 1 3 MBK116 3 MBK091 Top view 1 2 3 SOT78 (TO-220AB) [1] SOT404 (D2-PAK) SOT428 (D-PAK) It is not possible to make connection to pin 2 of the SOT404 and SOT428 packages. Philips Semiconductors PHP/PHB/PHD55N03LTA TrenchMOS™ Logic Level FET 5. Quick reference data Table 2: VDS ID Ptot Tj RDSon Quick reference data Conditions 25 °C ≤ Tj ≤ 175 °C Tmb = 25 °C; VGS = 5 V Tmb = 25 °C VGS = 10 V; ID = 25 A; Tj = 25 °C VGS = 5 V; ID = 25 A; Tj = 25 °C Typ 11 15 Max 25 55 85 175 14 18 Unit V A W °C mΩ mΩ drain-source voltage (DC) drain current (DC) total power dissipation junction temperature drain-source on-state resistance Symbol Parameter 6. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR ID VGS IDM Ptot Tstg Tj IS ISM drain-source voltage (DC) drain-gate voltage (DC) drain current (DC) gate-source voltage peak drain current total power dissipation storage temperature junction temperature source (diode forward) current (DC) Tmb = 25 °C peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs unclamped inductive load; ID = 25 A; tp = 0.1 ms; VDD = 15 V; RGS = 50 Ω; VGS = 5V; starting Tj = 25 °C Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 Tmb = 25 °C; Figure 1 Conditions 25 °C ≤ Tj ≤ 175 °C 25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ Tmb = 25 °C; VGS = 5 V; Figure 2 and 3 Tmb = 100 °C; VGS = 5 V; Figure 2 Min −55 −55 Max 25 25 55 38 ±20 220 85 +175 +175 55 220 60 Unit V V A A V A W °C °C A A mJ Source-drain diode Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy 9397 750 10143 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 — 4 September 2002 2 of 14 Philips Semiconductors PHP/PHB/PHD55N03LTA TrenchMOS™ Logic Level FET 120 Pder (%) 80 03aa16 120 Ider (%) 80 03aa24 40 40 0 0 50 100 150 200 Tmb (° C) 0 0 50 100 150 200 Tmb (° C) P tot P der = ---------------------- × 100 % P ° tot ( 25 C ) ID I der = ------------------ × 100 % I ° D ( 25 C ) Fig 1. Normalized total power dissipation as a function of mounting base temperature. Fig 2. Normalized continuous drain current as a function of mounting base temperature. 103 ID (A) 03ae64 Limit RDSon = VDS / ID tp = 10 µs 102 100 µs 10 DC 1 ms 10 ms 100 ms 1 1 10 VDS (V) 102 Tmb = 25 °C; IDM is single pulse. Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. 9397 750 10143 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 — 4 September 2002 3 of 14 Philips Semiconductors PHP/PHB/PHD55N03LTA TrenchMOS™ Logic Level FET 7. Thermal characteristics Table 4: Rth(j-mb) Rth(j-a) Thermal characteristics Conditions Min Typ Max Unit 60 75 50 1.75 K/W K/W K/W K/W thermal resistance from junction to mounting base Figure 4 thermal resistance from junction to ambient SOT78 SOT428 SOT404 and SOT428 vertical in still air SOT428 minimum footprint; mounted on a PCB SOT404 minimum footprint; mounted on a PCB Symbol Parameter 7.1 Transient thermal impedance 10 Zth(j-mb) (K/W) 03ae63 1 δ = 0.5 0.2 0.1 10-1 0.05 0.02 P δ= tp T single pulse 10-2 10-5 tp T 10-4 10-3 10-2 10-1 t tp (s) 1 Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration. 9397 750 10143 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 — 4 September 2002 4 of 14 Philips Semiconductors PHP/PHB/PHD55N03LTA TrenchMOS™ Logic Level FET 8. Characteristics Table 5: Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Static characteristics V(BR)DSS drain-source breakdown voltage ID = 0.25 mA; VGS = 0 V Tj = 25 °C Tj = −55 °C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9 Tj = 25 °C Tj = 175 °C Tj = −55 °C IDSS drain-source leakage current VDS = 25 V; VGS = 0 V Tj = 25 °C Tj = 175 °C IGSS RDSon gate-source leakage current drain-source on-state resistance VGS = ±5 V; VDS = 0 V VGS = 5 V; ID = 25 A; Figure 7 and 8 Tj = 25 °C Tj = 175 °C VGS = 10 V; ID = 25 A Tj = 25 °C Dynamic characteristics gfs Qg(tot) Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf VSD forward transconductance total gate charge gate-source charge gate-dra.


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