GS81032AT

GS81032AT/Q-150/138/133/117/100/66 TQFP, QFP Commercial Temp Industrial Temp Features FT pin for user-configurable flow through or pipeline operation Single Cycle Deselect (SCD) operation 3.3 V +10%/–5% core power supply 2.5 V or 3.3 V I/O supply LBO pin for Linear or Interleaved Burst mode Internal input resistors on mode pins allow floating mode pins Default to Interleaved Pipeline mode Byte Write (BW) and/or Global Write (GW) operation Common data inputs and data outputs Clock Control, registered, address, data, and control Internal self-timed write cycle Automatic power-down for portable applications JEDEC-standard 100-lead TQFP or QFP package -150 Pipeline tCycle 6.6 3-1-1-1 tKQ 3.8 IDD 270 Flow tCycle 10.5 Through tKQ 9 2-1-1-1 IDD 170 -138 -133 7.25 7.5 4 4 245 240 15 15 9.7 10 120 120 -117 8.5 4.5 210 15 11 120 -100 10 5 180 15 12 120 -66 12.5 6 150 20 18 95 Unit ns ns mA ns ns mA 32K x 32 1M Synchronous Burst SRAM Flow Through/Pipeline Reads 150 MHz–66 MHz 9 ns–18 ns 3.3 V VDD 3.3 V and 2.5 V I/O The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register. SCD Pipelined Reads The GS81032A is an SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect)...