PCK2509S

INTEGRATED CIRCUITS PCK2509S 50–150 MHz 1:9 SDRAM clock driver Product specification 1999 Oct 19 Philips Semiconductors Philips Semiconductors Product specification 50–150 MHz 1:9 SDRAM clock driver PCK2509S FEATURES Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM applications Spread Spectrum clock compatible Operating frequency 50 to 150 MHz (tphase error – jitter) at 100 to133 MHz = ±50 ps Jitter (peak-peak) at 100 to 133 MHz = ± 80 ps Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps Pin-to-pin skew < 200 ps Available in plastic 24-Pin TSSOP Distributes one clock input to one bank of ten outputs External Feedback (FBIN) terminal Is used to synchronize the outputs to the clock input adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic–low state. Unlike many products containing PLLs, the PCK2509S does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the PCK2509S requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal a...