CMOS Programmable peripheral Interface
Features
• Pin Compatible with NMOS 8255A • 24 Programmable I/O Pins • Fully TTL Compatible • High Speed, No “Wait State” Operation with 5MHz 80C86 and 8MHz 80C88 • Direct Bit Set/Reset Capability • Enhanced Control Word Read Capability • L7 Process • 2.5mA Drive Capability on All I/O Ports • Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . .10µA
WS82C55A
Description
The WS82C55A is a high performance CMOS version of the industry standard 8255A and is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). It is a general purpose programmable I/O device which may be used with many different microprocessors. There are 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. The high performance and industry standard configuration of the WS82C55A make it compatible with the 80C86, and other microprocessors. Static CMOS circuit design insures low operating power. TTL compatibility over the full military temperature range and bus hold circuitry eliminate the need for pull-up resistors. The advanced SAJI process results in performance equal to or greater than existing functionally equivalent products at a fraction of the power.
SPEED
Ordering Information
PART NUMBERS
SPEED
PART NUMBERS
TEMPERATURE RANGE
o
PKG.
40DIP 44 PLCC 44 QFP
WS82C55A-5P
5MHz
WS82C55AP
8MHz
8MHz
0 C to 70 C
o
o
WS82C55A-5C
WS82C55A-5Q
5MHz
5MHz
WS82C55AC
WS82C55AQ
0 C to 70 C
o
8MHz
0 C to 70 C
o
o
Pinouts
44 RD 43 PA0 42 PA1 41 PA2 40 PA3 38 PA4 37 PA5 36 PA6 35 PA7 34 WR 39 VCC
PA3 PA2 PA1 PA0 RD CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 40 39 38 37 36 5 35 6 7 WS82C55A-5P 34 8 WS82C55AP 33 32 9 10 31 11 30 12 29 1 2 3 4 13 14 15 16 17 18 19 20 PA4 PA5 PA6 CS 1 PA7 WR GND 2 RESET A1 3 D0 A0 4 D1 PC7 5 D2 PC6 6 D3 D4 PC5 7 D5 PC4 8 D6 PC0 9 D7 PC1 10 VCC PC2 11 PB7 PB6 PB5 PB4 PB3 RD PA0 PA1 PA2 PA3 NC PA4 PA5 PA6 PA7 WR 6 5 4 3 2 1 44 43 42 41 40
WS82C55A-5Q WS82C55AQ
QFP-44
DIP-40
28 27 26 25 24 23 22 21
PC2 PC3 PB0 PB1
NC 12 PC3 13 PB0 14
PB1 15 PB2 16
17
PB3 18 PB4 19 PB5 20
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
Wing Shing Computer Components Co., (H.K.)Ltd. Homepage: http://www.wingshing.com Tel:(852)2341 9276 Fax:(852)2797 8153 E-mail:
[email protected]
PB6 21 NC 22
VCC
PB2 NC PB3 PB4 PB5 PB6 PB7
33 32 31 30 29 28 27 26 25 24 23
RESET D0 D1 D2. D3 D4 D5 D6 D7 VCC PB7
CS GND A1 A0 PC7 NC PC6 PC5 PC4 PC0 PC1
7 8 9 10 11 12 13 14 15 16 17
WS82C55A-5C
WS82C55AC
PLCC-44
39 38 37 36 35 34 33 32 31 30 29
RESET D0 D1 D2 D3 NC D4 D5 D6 D7 VCC
18 1920 21 22 23 24 25 26 27 28
WS82C55A
Pin Description ( For DIP-40)
SYMBOL VCC GND D0-D7 RESET CS RD WR A0-A1 PIN NUMBER 26 7 27-34 35 6 5 36 8, 9 I/O I I I I I TYPE DESCRIPTION VCC: The +5V power supply pin. A 0.1µF capacitor between pins 26 and 7 is recommended for decoupling. GROUND DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus. RESET: A high on this input clears the control register and all ports (A, B, C) are set to the input mode with the “Bus Hold” circuitry turned on. CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU communications. READ: Read is an active low input control signal used by the CPU to read status information or data via the data bus. WRITE: Write is an active low input control signal used by the CPU to load control words and data into the 82C55A. ADDRESS: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus A0, A1. PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are present on this port. PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port. PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.
PA0-PA7 PB0-PB7 PC0-PC7
1-4, 37-40 18-25 10-17
I/O I/O I/O
Functional Diagram
POWER SUPPLIES
+5V GND GROUP A CONTROL
GROUP A PORT A (8)
I/O PA7-PA0
BI-DIRECTIONAL DATA BUS D7-D0 DATA BUS BUFFER 8-BIT INTERNAL DATA BUS
GROUP A PORT C UPPER (4) GROUP B PORT C LOWER (4)
I/O PC7-PC4
I/O PC3-PC0
RD WR A1 A0 RESET
READ WRITE CONTROL LOGIC
GROUP B CONTROL
GROUP B PORT B (8)
I/O PB7-PB0
CS
2
WS82C55A
Functional Description
Data Bus Buffer This three-state bi-directional 8-bit buffer is used to interface WS82C55A to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. Read/Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. .