WL102B

WL102B Wireless Data Controller Advance Information DS4582 - 3.0 July 1999 Features q Ordering Information WL102B/IG/TP1R 100 pin package WL102BC/PR/FP1R 144 pin package Complete CMOS, single chip, radio transceiver controller Hardware implemented Communication Control Block (CCB) Protocol independent design using external flash memory Internal 8051 and external processor options Internal/external buffer and processor RAM Block power down facility PCMCIA/8bit processor host interface to buffer RAM Up to 1Mbps/2 level or 2 Mbps/4 level operation q q q q q q The WL102B is a highly integrated CMOS wireless data controller designed to dramatically reduce the cost of radio data applications. It works with the WL600C RF IF chip and WL800 synthesiser chip to offer a complete solution for a frequency hopping, spread spectrum radio in the 2.4 to 2.45GHz ISM band. Its flexible design means that it can also be used in a wide range of other applications using a range of "processor", protocols and additional memory options as well as radios at other frequencies. q Related Documents WL600C, WL800 and WL102B (DS4837) Datasheets Receive Transmit DMA Status Control Communications Control Block Memory Control Block Buffer RAM 6K4 Interrupt Address Data Control Address Data Control Port Pins Interrupt 8051 System RAM 4K Counters Power Down Control Attribute Memory WL102 Configuration Figure 1 WL102 Minimum configuration block diagram WL102 Advance Information HD1 HD0 HA1 HRE...