Document
W986416DH
GENERAL DESCRIPTION
1M × 4 BANKS × 16 BITS SDRAM
W986416DH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 1M words × 4 banks × 16 bits. Using pipelined architecture and 0.175 µm process technology, W986416DH delivers a data bandwidth of up to 366M bytes per second (-55). For different application, W986416DH is sorted into the following speed grades: –55, -6, -7. The -55 parts can run up to 183 MHz/CL3. The -6 parts can run up to 166 MHz/CL3. The -7 parts can run up to 143 MHz/CL3. For handheld device application, we also provide a low power option, the grade of –7L, with Self Refresh Current under 400 µA and work well at 2.7V during Self Refresh Mode.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W986416DH is ideal for main memory in high performance applications.
FEATURES
• 3.3V ±0.3V power supply • 1048576 words × 4 banks × 16 bits organization • Self Refresh Current: Standard and Low Power • CAS latency: 2 and 3 • Burst Length: 1, 2, 4, 8, and full page • Sequential and Interleave burst • Burst read, single write operation • Byte data controlled by DQM • Power-down Mode • Auto-precharge and controlled precharge • 4K refresh cycles/64 mS • Interface: LVTTL • Packaged in TSOP II 54-pin, 400 mil - 0.80
AVAILABLE PART NUMBER
PART NUMBER SPEED (CL = 3)
W986416DH-55 W986416DH-6 W986416DH-7 W986416DH-7L
183 MHz 166 MHz 143 MHz 143 MHz
SELF REFRESH CURRENT (MAX.)
1 mA 1 mA 1 mA 400 µA
POWER SUPPLY FOR SELF REFRESH MODE
3.0V - 3.6V 3.0V - 3.6V 3.0V - 3.6V 2.7V - 3.6V
Publication Release Date: June 2001 - 1 - Revision A2
PIN CONFIGURATION
V CC DQ0
V CC Q DQ1 DQ2 V SS Q DQ3 DQ4 V CC Q DQ5 DQ6 V SS Q DQ7
V CC LDQM
WE CAS RAS
CS BS0 BS1 A10/AP
A0 A1 A2 A3 V CC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
W986416DH
54 VSS 53 DQ15 52 VSSQ 51 DQ14 50 DQ13 49 V CC Q 48 DQ12 47 DQ11 46 VSSQ 45 DQ10 44 DQ9 43 VCC Q 42 DQ8 41 VSS 40 NC 39 UDQM 38 CLK 37 CKE 36 NC 35 A11 34 A9 33 A8 32 A7 31 A6 30 A5 29 A4 28 VSS
-2-
W986416DH
PIN DESCRIPTION
PIN NUMBER PIN NAME FUNCTION
23 ~ 26, 22, 29 ~35
A0−A11
Address
20, 21
BS0, BS1 Bank Select
2, 4, 5, 7, 8, 10, DQ0−DQ15 Data Input/
11, 13, 42, 44,
Output
45, 47, 48, 50,
51, 53
19 CS Chip Select
18
RAS
Row Address
Strobe
17
CAS
Column
Address
Strobe
16 WE Write Enable
DESCRIPTION Multiplexed pins for row and column address. Row address: A0−A11. Column address: A0−A7. A10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by BS0, BS1. Select bank to activate during row address latch time, or bank to read/write during address latch time. Multiplexed pins for data output and input.
Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Command input. When sampled at the rising edge of the clock RAS , CAS and WE define the operation to be executed. Referred to RAS
Referred to RAS
39, 15
38 37
UDQM LDQM
CLK CKE
1, 14, 27 28, 41, 54 3, 9, 43, 49
VCC VSS VCCQ
6, 12, 46, 52 VSSQ
36, 40
NC
Input/output mask
The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency.
Clock Inputs System clock used to sample inputs on the rising edge of clock.
Clock Enable CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered.
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
Ground
Ground for input buffers and logic circuit inside DRAM.
Power (+3.3V) Separated power from VCC, to improve DQ noise for I/O buffer immunity.
Ground for I/O Separated ground from VSS, to improve DQ noise
buffer
immunity.
No Connection No connection
Publication Release Date: June 2001 - 3 - Revision A2
BLOCK DIAGRAM
W986416DH
CLK
CKE
CS RAS CAS WE
CLOCK BUFFER
COMMAND DECODER
CONTROL SIGNAL
GENERATOR
A10
A0 MODE REGISTER
A9 ADDRESS A11 BUFFER BS0 BS1
REFRESH COUNTER
COLUMN COUNTER
COLUMN DECODER CELL ARRAY BANK #0
SENSE AMPLIFIER
DATA CONTROL CIRCUIT
COLUMN DECODER CELL ARRAY BANK #2
SENSE AMPLIFIER
ROW DECODER ROW DECODER
ROW DECODER ROW DECODER
COLUMN DECODER
CELL ARRAY BANK #1
SENSE AMPLIFIER
DQ BUFFER
COLUMN DECODER CELL ARRAY BANK #3
SENSE A.