W986416CH

W986416CH 1M x 16 bit x 4 Banks SDRAM Features 3.3V±0.3V power supply Up to 166 MHz clock frequency 1,048,576 words x 4 banks x 16 bits organization Auto Refresh and Self Refresh CAS latency: 2 and 3 Burst Length: 1, 2, 4, 8 , and full page Burst read, Single Writes Mode Byte data controlled by UDQM and LDQM Power-Down Mode Auto-Precharge and controlled precharge 4k refresh cycles / 64ms Interface: LVTTL Package: TSOP II 54 pin, 400 mil - 0.80 General Description W986416CH is a high speed synchronous dynamic random access memory (SDRAM), organized as 1M words x 4 banks x 16 bits. Using pipelined architecture and 0.20um process technology, W986416CH delivers a data bandwidth of up to 332M bytes per second (-6). For different application, W986416CH is sorted into four speed grades: -6, -7, -75 and -8H. The -6 parts can run up to 166Mhz/CL3. The -7 parts can run up to 143Mhz/CL3 specification. The -75 parts can run up to PC133/CL3 specification. The -8H parts can run up to 125Mhz/CL3 or PC100/CL2 specification. Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide ...