W40S11-23

W40S11-23 Clock Buffer/Driver Features Thirteen skew-controlled CMOS clock outputs (SDRAM0:12) Supports three SDRAM DIMMs Ideal for high-performance systems designed around Intel’s latest chip set I2C serial configuration interface Clock Skew between any two outputs is less than 250 ps 1- to 5-ns propagation delay DC to 133-MHz operation Single 3.3V supply voltage Low power CMOS design packaged in a 28-pin, 300-mil SOIC (Small Outline Integrated Circuit) Key Specifications Supply Voltages:........................................... VDD = 3.3V±5% Operating Temperature:.................................... 0°C to +70°C Input Threshold: .................................................. 1.5V typical Maximum Input Voltage: .......................................VDD + 0.5V Input Frequency:............................................... 0 to 133 MHz BUF_IN to SDRAM0:12 Propagation Delay: ...... 1.0 to 5.0 ns Output Edge Rate:.............................................. >1.5 V/ns Output Clock Skew: .................................................. ±250 ps Output Duty Cycle: .................................. 45/55% worst case Output Impedance: ...............................................15Ω typical Output Type: ................................................ CMOS rail-to-rail Overview The Cypress W40S11-23 is a low-voltage, thirteen-output clock buffer. Output buffer impedance is approximately 15Ω, which is ideal for driving SDRAM DIMMs. Block Diagram Pi...