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W25S243A Dataheets PDF



Part Number W25S243A
Manufacturers Winbond
Logo Winbond
Description 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM
Datasheet W25S243A DatasheetW25S243A Datasheet (PDF)

Preliminary W25S243A 64K × 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM GENERAL DESCRIPTION The W25S243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM organized as 65,536 × 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst address counter supports both Pentium™ burst mode and linear burst mode. The mode to be executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by the FT pin. A snooze mod.

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Preliminary W25S243A 64K × 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM GENERAL DESCRIPTION The W25S243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM organized as 65,536 × 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst address counter supports both Pentium™ burst mode and linear burst mode. The mode to be executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by the FT pin. A snooze mode can reduces power dissipation. This device supports 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle. FEATURES • • • • • • • Synchronous operation High-speed access time: 12 nS Single +3.3V power supply Individual byte write capability 3.3V LVTTL compatible I/O Clock-controlled and registered input Asynchronous output enable • • • • • Pipelined/non-pipelined data output capability Supports snooze mode (low-power state) Internal burst counter supports Intel burst (Interleaved) mode & linear burst mode Supports 2T/1T mode Packaged in 128-pin QFP and TQFP BLOCK DIAGRAM A(15:0) INPUT REGISTER 64K X 64 CORE ARRAY CLK CE(3:1) GW BWE BW(8:1) OE ADSC ADSP ADV LBO FT ZZ CONTROL LOGIC REGISTER DATA I/O REGISTER I/O(64:1) -1- Publication Release Date: November 1998 Revision A1 Preliminary W25S243A PIN CONFIGURATION V D C D NEN Q C2 C 1 1 2 2 8 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 3 9 / / / / / CV V/ B BB B/ C E S D C W W W WO L 3 S DE8 7 6 5 EK / / / / / AA/ V / / B / BBVV B BDDAS W G WWS D W WS S D S E W4 3 S D 2 1 C P V Q VSSQ I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 I/O40 I/O41 I/O42 I/O43 VDDQ VSSQ I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 VDDQ VSSQ I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I/O64 VDDQ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 102 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 65 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 / AA AV VAA A AA RAA AAA VVAA A Z V L 1 1 1 DS1 1 1 9 8 S 7 6 5 4 3 DS 2 1 0 Z D V D B54 3 DS2 1 0 DS Q O VDDQ I/O32 I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 I/O23 I/O22 VSSQ VDDQ I/O21 I/O20 I/O19 I/O18 I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 VSSQ VDDQ I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 VSSQ V/ SF ST Q -2- Preliminary W25S243A PIN DESCRIPTION SYMBOL A0−A15 I/O1−I/O64 CLK CE1, CE2, CE3 GW BWE BW1 − BW8 OE ADV ADSC ADSP ZZ FT TYPE Input, Synchronous I/O, Synchronous Input, Clock Input, Synchronous Input, Synchronous Input, Synchronous Input, Synchronous Input, Asynchronous Input, Synchronous Input, Synchronous Input, Synchronous Input, Asynchronous Input, Static Host address Data Inputs/Outputs Processor host bus clock Chip enables Global write Byte write enable from cache controller Host bus byte enables used with BWE Output enable input Internal burst address counter advance Address status from Chip Set Address status from CPU Snooze pin for low-power state, internal pull low Connected to VSSQ: Device operates in flowthrough (non-pipelined) mode. Connected to VDDQ or unconnected: Device operates in pipelined mode. LBO Input, Static Lower address burst order Connected to VSSQ: Device is in linear mode. Connected to VDDQ or unconnected: Device is in non-linear mode. VDDQ VSSQ VDD VSS RSV NC I/O power supply I/O ground Power supply Ground Reserved pin, don't use these pins No connection DESCRIPTION -3- Publication Release Date: November 1998 Revision A1 Preliminary W25S243A FUNCTIONAL DESCRIPTION The W25S243A is a synchronous-burst pipelined SRAM designed for use in high-end personal computers. It supports two burst address sequences for Intel™ systems (Interleaved mode) and linear mode, which can be controlled by the LBO pin. The burst cycles are initiated by ADSP or ADSC and the burst counter is incremented whenever ADV is sampled low. The device can also be switched to non-pipelined mode if necessary. BURST ADDRESS SEQUENCE INTEL SYSTEM ( LBO = VDDQ) A[1:0] External Start Address Second Address Third Address Fourth Address 00 01 10 11 A[1:0] 01 00 11 10 A[1:0] 10 11 00 01 A[1:0] 11 10 01 00 LINEAR MODE ( LBO = VSSQ) A[1:0] 00 01 10 11 A[1:0] 01 10 11 00 A[1:0] 10 11 00 01 A[1:0] 11 00 01 10 The device supports several types of write mode operations. BWE and BW [8:1] support individual byte writes. The BE [7:0] signals can be directly connected to the SRAM BW [8:1]. The GW signal is used to override the byte enable signals and allows the cache controller to write all bytes to the SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the SRAM with addresses but wit.


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